regkeys

FPGA之间的LVDS传输

NUM_PROPERTIES
168
s
prop_100_name
PROP_TopDesignUnit
s
prop_100_val
""
s
prop_101_name
PROP_TopDesignUnit
s
prop_101_val
""
s
prop_102_name
PROP_TopDesignUnit
s
prop_102_val
""
s
prop_103_name
PROP_TopDesignUnit
s
prop_103_val
""
s
prop_104_name
PROP_xstVeriIncludeDir
s
prop_104_val
""
s
prop_105_name
PROP_DevFamily
s
prop_105_val
"Automotive CoolRunner2"
s
prop_106_name
PROP_Simulator
s
prop_106_val
"Modelsim-SE Mixed"
s
prop_107_name
PROP_SmartGuideFileName
s
prop_107_val
"_guide.ncd"
s
prop_108_name
PROP_vsim_otherCmdLineOptions
s
prop_108_val
""
s
prop_109_name
PROP_vlog_otherCmdLineOptions
s
prop_109_val
""
s
prop_10_name
PROP_DesignName
s
prop_10_val
"xlnx_auto_0"
s
prop_110_name
PROP_vcom_otherCmdLineOptions
s
prop_110_val
""
s
prop_111_name
PROP_ModelSimSignalWin
s
prop_111_val
"true"
s
prop_112_name
PROP_ModelSimWaveWin
s
prop_112_val
"true"
s
prop_113_name
PROP_ModelSimStructWin
s
prop_113_val
"true"
s
prop_114_name
PROP_ModelSimSourceWin
s
prop_114_val
"false"
s
prop_115_name
PROP_ModelSimListWin
s
prop_115_val
"false"
s
prop_116_name
PROP_ModelSimVarsWin
s
prop_116_val
"false"
s
prop_117_name
PROP_ModelSimProcWin
s
prop_117_val
"false"
s
prop_118_name
PROP_ModelSimDataWin
s
prop_118_val
"false"
s
prop_119_name
PROP_ModelSimSimRes
s
prop_119_val
"Default (1 ps)"
s
prop_11_name
PROP_Dummy
s
prop_11_val
"dum1"
s
prop_120_name
PROP_SimSyntax
s
prop_120_val
"93"
s
prop_121_name
PROP_SimUseExpDeclOnly
s
prop_121_val
"true"
s
prop_122_name
PROP_ModelSimSimRunTime_tb
s
prop_122_val
"1000ns"
s
prop_123_name
PROP_ModelSimUutInstName_postFit
s
prop_123_val
"UUT"
s
prop_124_name
PROP_SimGenVcdFile
s
prop_124_val
"false"
s
prop_125_name
PROP_SimCustom_behav
s
prop_125_val
""
s
prop_126_name
PROP_SimUserCompileList_behav
s
prop_126_val
""
s
prop_127_name
PROP_SimCustom_postPar
s
prop_127_val
""
s
prop_128_name
PROP_ModelSimSimRunTime_tbw
s
prop_128_val
"1000ns"
s
prop_129_name
PROP_ModelSimConfigName
s
prop_129_val
"Default"
s
prop_12_name
PROP_SimUseCustom_behav
s
prop_12_val
"false"
s
prop_130_name
PROP_SimModelRenTopLevInstTo
s
prop_130_val
"UUT"
s
prop_131_name
PROP_SynthConstraintsFile
s
prop_131_val
""
s
prop_132_name
PROP_impactPort
s
prop_132_val
"Auto - default"
s
prop_133_name
PROP_XPowerOptMaxNumberLines
s
prop_133_val
"1000"
s
prop_134_name
PROP_xstSafeImplement
s
prop_134_val
"No"
s
prop_135_name
PROP_FitterOptimization_xpla3
s
prop_135_val
"Density"
s
prop_136_name
PROP_xcpldFitDesPtermLmt_xbr
s
prop_136_val
"28"
s
prop_137_name
PROP_xcpldFitDesInReg_xbr
s
prop_137_val
"true"
s
prop_138_name
PROP_DevFamilyPMName
s
prop_138_val
"acr2"
s
prop_139_name
PROP_DevDevice
s
prop_139_val
"xa2c*"
s
prop_13_name
PROP_SimDo
s
prop_13_val
"true"
s
prop_140_name
PROP_CompxlibSimPath
s
prop_140_val
"c:/Modeltech_6.1f/win32"
s
prop_141_name
PROP_CompxlibLang
s
prop_141_val
"All"
s
prop_142_name
PROP_SimModelGenMultiHierFile
s
prop_142_val
"false"
s
prop_143_name
PROP_DevPackage
s
prop_143_val
"*"
s
prop_144_name
PROP_Synthesis_Tool
s
prop_144_val
"XST (VHDL/Verilog)"
s
prop_145_name
PROP_CompxlibUniSimLib
s
prop_145_val
"true"
s
prop_146_name
PROP_CompxlibUni9000Lib
s
prop_146_val
"true"
s
prop_147_name
PROP_DevSpeed
s
prop_147_val
"-*"
s
prop_148_name
PROP_PreferredLanguage
s
prop_148_val
"Verilog"
s
prop_149_name
PROP_SimModelTarget
s
prop_149_val
"Verilog"
s
prop_14_name
PROP_SimUseCustom_postPar
s
prop_14_val
"false"
s
prop_150_name
PROP_tbwTestbenchTargetLang
s
prop_150_val
"Verilog"
s
prop_151_name
PROP_SimModelRenTopLevArchTo
s
prop_151_val
"Structure"
s
prop_152_name
PROP_SimModelGenArchOnly
s
prop_152_val
"false"
s
prop_153_name
PROP_SimModelOutputExtIdent
s
prop_153_val
"false"
s
prop_154_name
PROP_SimModelRenTopLevMod
s
prop_154_val
""
s
prop_155_name
PROP_SimModelIncUselibDirInVerilogFile
s
prop_155_val
"false"
s
prop_156_name
PROP_SimModelIncSdfAnnInVerilogFile
s
prop_156_val
"true"
s
prop_157_name
PROP_SimModelNoEscapeSignal
s
prop_157_val
"false"
s
prop_158_name
PROP_netgenPostParSimModelName
s
prop_158_val
"_timesim.v"
s
prop_159_name
PROP_bencherPostParTestbenchName
s
prop_159_val
""
s
prop_15_name
PROP_ModelSimUseConfigName
s
prop_15_val
"false"
s
prop_160_name
PROP_SimModelIncSimprimInVerilogFile
s
prop_160_val
"false"
s
prop_161_name
PROP_SimModelAutoInsertGlblModuleInNetlist
s
prop_161_val
"true"
s
prop_162_name
PROP_PostParSimModelName
s
prop_162_val
"_timesim.v"
s
prop_163_name
PROP_PostParSimModelName
s
prop_163_val
"_timesim.v"
s
prop_164_name
PROP_tbwPostParTestbenchName
s
prop_164_val
""
s
prop_165_name
PROP_tbwPostParTestbenchName
s
prop_165_val
""
s
prop_166_name
PROP_SimModelBringOutGsrNetAsAPort
s
prop_166_val
"false"
s
prop_167_name
PROP_netgenRenameTopLevEntTo
s
prop_167_val
""
s
prop_168_name
PROP_SimModelPathUsedInSdfAnn
s
prop_168_val
"Default"
s
prop_16_name
PROP_MSimSDFTimingToBeRead
s
prop_16_val
"Setup Time"
s
prop_17_name
PROP_CompxlibOutputDir
s
prop_17_val
"$XILINX/<language>/<simulator>"
s
prop_18_name
PROP_CompxlibOverwriteLib
s
prop_18_val
"Overwrite"
s
prop_19_name
PROP_CompxlibOtherCompxlibOpts
s
prop_19_val
""
s
prop_1_name
PROP_Parse_Target
s
prop_1_val
"synthesis"
s
prop_20_name
PROP_CompxlibSimPrimatives
s
prop_20_val
"true"
s
prop_21_name
PROP_SimModelGenerateTestbenchFile
s
prop_21_val
"false"
s
prop_22_name
PROP_SimModelOtherNetgenOpts
s
prop_22_val
""
s
prop_23_name
PROP_SimModelRetainHierarchy
s
prop_23_val
"true"
s
prop_24_name
PROP_SynthOpt
s
prop_24_val
"Speed"
s
prop_25_name
PROP_SynthOptEffort
s
prop_25_val
"Normal"
s
prop_26_name
PROP_xstUseSynthConstFile
s
prop_26_val
"true"
s
prop_27_name
PROP_xstLibSearchOrder
s
prop_27_val
""
s
prop_28_name
PROP_xstCase
s
prop_28_val
"Maintain"
s
prop_29_name
PROP_xstWorkDir
s
prop_29_val
"./xst"
s
prop_2_name
PROP_Top_Level_Module_Type
s
prop_2_val
"HDL"
s
prop_30_name
PROP_xstIniFile
s
prop_30_val
""
s
prop_31_name
PROP_xstVerilog2001
s
prop_31_val
"true"
s
prop_32_name
PROP_xstVeriIncludeDir_Global
s
prop_32_val
""
s
prop_33_name
PROP_xstUserCompileList
s
prop_33_val
""
s
prop_34_name
PROP_xstGenericsParameters
s
prop_34_val
""
s
prop_35_name
PROP_xstVerilogMacros
s
prop_35_val
""
s
prop_36_name
PROP_xst_otherCmdLineOptions
s
prop_36_val
""
s
prop_37_name
PROP_xstGenerateRTLNetlist
s
prop_37_val
"Yes"
s
prop_38_name
PROP_xstHierarchySeparator
s
prop_38_val
"/"
s
prop_39_name
PROP_xstBusDelimiter
s
prop_39_val
"<>"
s
prop_3_name
PROP_SynthTop
s
prop_3_val
""
s
prop_40_name
PROP_SynthFsmEncode
s
prop_40_val
"Auto"
s
prop_41_name
PROP_SynthCaseImplStyle
s
prop_41_val
"None"
s
prop_42_name
PROP_SynthResSharing
s
prop_42_val
"true"
s
prop_43_name
PROP_SynthExtractMux
s
prop_43_val
"Yes"
s
prop_44_name
PROP_xilxSynthAddIObuf
s
prop_44_val
"true"
s
prop_45_name
PROP_xstEquivRegRemoval
s
prop_45_val
"true"
s
prop_46_name
PROP_ibiswriterShowAllModels
s
prop_46_val
"false"
s
prop_47_name
PROP_ImpactProjectFile
s
prop_47_val
"Default"
s
prop_48_name
PROP_ngdbuild_otherCmdLineOptions
s
prop_48_val
""
s
prop_49_name
PROP_xilxNgdbld_AUL
s
prop_49_val
"false"
s
prop_4_name
PROP_BehavioralSimTop
s
prop_4_val
""
s
prop_50_name
PROP_xilxNgdbldMacro
s
prop_50_val
""
s
prop_51_name
PROP_xilxSynthKeepHierarchy
s
prop_51_val
"No"
s
prop_52_name
PROP_xstNetlistHierarchy
s
prop_52_val
"As Optimized"
s
prop_53_name
PROP_XPowerOptVerboseRpt
s
prop_53_val
"false"
s
prop_54_name
PROP_XPowerOptLoadXMLFile
s
prop_54_val
"Default"
s
prop_55_name
PROP_XPowerOptOutputFile
s
prop_55_val
"Default"
s
prop_56_name
PROP_XPowerOptLoadVCDFile
s
prop_56_val
"Default"
s
prop_57_name
PROP_XPowerOptInputTclScript
s
prop_57_val
""
s
prop_58_name
PROP_XPowerOtherXPowerOpts
s
prop_58_val
""
s
prop_59_name
PROP_UserEditorPreference
s
prop_59_val
"ISE Text Editor"
s
prop_5_name
PROP_PostParSimTop
s
prop_5_val
""
s
prop_60_name
PROP_UserEditorCustomSetting
s
prop_60_val
""
s
prop_61_name
PROP_UserConstraintEditorPreference
s
prop_61_val
"Constraints Editor"
s
prop_62_name
PROP_FlowDebugLevel
s
prop_62_val
"0"
s
prop_63_name
PROP_FitterReportFormat
s
prop_63_val
"HTML"
s
prop_64_name
PROP_Enable_Message_Capture
s
prop_64_val
"true"
s
prop_65_name
PROP_Enable_Message_Filtering
s
prop_65_val
"false"
s
prop_66_name
PROP_Enable_Incremental_Messaging
s
prop_66_val
"false"
s
prop_67_name
PROP_lockPinsUcfFile
s
prop_67_val
""
s
prop_68_name
PROP_EnableWYSIWYG
s
prop_68_val
"None"
s
prop_69_name
PROP_xcpldUseLocConst
s
prop_69_val
"Always"
s
prop_6_name
PROP_PostFitSimTop
s
prop_6_val
""
s
prop_70_name
PROP_xcpldFitDesInit
s
prop_70_val
"Low"
s
prop_71_name
PROP_xcpldFitDesTimingCst
s
prop_71_val
"true"
s
prop_72_name
PROP_CPLDFitkeepio
s
prop_72_val
"false"
s
prop_73_name
PROP_cpldBestFit
s
prop_73_val
"false"
s
prop_74_name
PROP_xcpldFitDesMultiLogicOpt
s
prop_74_val
"true"
s
prop_75_name
PROP_cpldfit_otherCmdLineOptions
s
prop_75_val
""
s
prop_76_name
PROP_fitGenSimModel
s
prop_76_val
"false"
s
prop_77_name
PROP_cpldfitHDLeqStyle
s
prop_77_val
"Source"
s
prop_78_name
PROP_xcpldFitDesSlew
s
prop_78_val
"Fast"
s
prop_79_name
PROP_xcpldUseGlobalClocks
s
prop_79_val
"true"
s
prop_7_name
PROP_UseSmartGuide
s
prop_7_val
"false"
s
prop_80_name
PROP_xcpldUseGlobalOutputEnables
s
prop_80_val
"true"
s
prop_81_name
PROP_xcpldUseGlobalSetReset
s
prop_81_val
"true"
s
prop_82_name
PROP_hprep6_autosig
s
prop_82_val
"false"
s
prop_83_name
PROP_hprep6_otherCmdLineOptions
s
prop_83_val
""
s
prop_84_name
PROP_xcpldFittimRptOption
s
prop_84_val
"Summary"
s
prop_85_name
PROP_taengine_otherCmdLineOptions
s
prop_85_val
""
s
prop_86_name
PROP_xilxSynthMacroPreserve
s
prop_86_val
"true"
s
prop_87_name
PROP_xilxSynthXORPreserve
s
prop_87_val
"true"
s
prop_88_name
PROP_xilxSynthKeepHierarchy_CPLD
s
prop_88_val
"Yes"
s
prop_89_name
PROP_PlsClockEnable
s
prop_89_val
"true"
s
prop_8_name
PROP_PartitionCreateDelete
s
prop_8_val
""
s
prop_90_name
PROP_CompxlibAbelLib
s
prop_90_val
"true"
s
prop_91_name
PROP_CompxlibCPLDDetLib
s
prop_91_val
"true"
s
prop_92_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr
s
prop_92_val
"false"
s
prop_93_name
PROP_xcpldFitTemplate_xpla3
s
prop_93_val
"Optimize Density"
s
prop_94_name
PROP_FunctionBlockInputLimit
s
prop_94_val
"38"
s
prop_95_name
PROP_xcpldFitDesInputLmt_xbr
s
prop_95_val
"32"
s
prop_96_name
PROP_xcpldFitDesUnused
s
prop_96_val
"Keeper"
s
prop_97_name
PROP_xcpldFitDesTriMode
s
prop_97_val
"Keeper"
s
prop_98_name
PROP_xcpldFitDesVolt
s
prop_98_val
"LVCMOS18"
s
prop_99_name
PROP_UseDataGate
s
prop_99_val
"true"
s
prop_9_name
PROP_PartitionForceSynth
s
prop_9_val
""
s