lvds_bist_top.twr

FPGA之间的LVDS传输

  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR (FF)
  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 (RAM)
  Requirement:          5.000ns
  Data Path Delay:      4.694ns (Levels of Logic = 0)
  Clock Path Skew:      -0.131ns (1.371 - 1.502)
  Source Clock:         CLK_DELAY rising at 0.000ns
  Destination Clock:    CLK_DELAY rising at 5.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.140ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR to U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36
    Location                Delay type         Delay(ns)  Physical Resource
                                                          Logical Resource(s)
    ----------------------------------------------------  -------------------
    SLICE_X45Y104.BQ        Tcko                  0.450   U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR<10>
                                                          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR
    RAMB36_X6Y21.ADDRBU13   net (fanout=43)       3.897   U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR<9>
    RAMB36_X6Y21.CLKBWRCLKU Trcck_ADDRB           0.347   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36
                                                          U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36
    ----------------------------------------------------  ---------------------------
    Total                                         4.694ns (0.797ns logic, 3.897ns route)
                                                          (17.0% logic, 83.0% route)

--------------------------------------------------------------------------------
Slack:                  0.081ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR (FF)
  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 (RAM)
  Requirement:          5.000ns
  Data Path Delay:      4.694ns (Levels of Logic = 0)
  Clock Path Skew:      -0.120ns (1.382 - 1.502)
  Source Clock:         CLK_DELAY rising at 0.000ns
  Destination Clock:    CLK_DELAY rising at 5.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.140ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR to U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36
    Location                Delay type         Delay(ns)  Physical Resource
                                                          Logical Resource(s)
    ----------------------------------------------------  -------------------
    SLICE_X45Y104.BQ        Tcko                  0.450   U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR<10>
                                                          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR
    RAMB36_X6Y21.ADDRBL13   net (fanout=43)       3.897   U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR<9>
    RAMB36_X6Y21.CLKBWRCLKL Trcck_ADDRB           0.347   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36
                                                          U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36
    ----------------------------------------------------  ---------------------------
    Total                                         4.694ns (0.797ns logic, 3.897ns route)
                                                          (17.0% logic, 83.0% route)

--------------------------------------------------------------------------------
Slack:                  0.091ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR (FF)
  Destination:          U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 (RAM)
  Requirement:          5.000ns
  Data Path Delay:      4.584ns (Levels of Logic = 0)
  Clock Path Skew:      -0.220ns (1.282 - 1.502)
  Source Clock:         CLK_DELAY rising at 0.000ns
  Destination Clock:    CLK_DELAY rising at 5.000ns
  Clock Uncertainty:    0.105ns

  Clock Uncertainty:          0.105ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.140ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR to U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36
    Location                Delay type         Delay(ns)  Physical Resource
                                                          Logical Resource(s)
    ----------------------------------------------------  -------------------
    SLICE_X45Y104.BQ        Tcko                  0.450   U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR<10>
                                                          U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR
    RAMB36_X5Y19.ADDRBL13   net (fanout=43)       3.787   U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR<9>
    RAMB36_X5Y19.CLKBWRCLKL Trcck_ADDRB           0.347   U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36
                                                          U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36
    ----------------------------------------------------  ---------------------------
    Total                                         4.584ns (0.797ns logic, 3.787ns route)
                                                          (17.4% logic, 82.6% route)

--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK_50M
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_50M        |    5.373|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 4447 paths, 0 nets, and 3467 connections

Design statistics:
   Minimum period:   5.373ns{1}   (Maximum frequency: 186.116MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Jan 11 23:20:17 2009 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 377 MB