📄 lvds_bist_top.twr
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Release 10.1.02 Trace (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle
ise -v 3 -s 1 -xml lvds_bist_top lvds_bist_top.ncd -o lvds_bist_top.twr
lvds_bist_top.pcf -ucf lvds_tx_rx_merge.ucf
Design file: lvds_bist_top.ncd
Physical constraint file: lvds_bist_top.pcf
Device,package,speed: xc5vfx130t,ff1738,-1 (ADVANCED 1.61 2008-05-28, STEPPING level 0)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_CLK100 = PERIOD TIMEGRP "CLK100" 10 ns HIGH 50%;
348 paths analyzed, 282 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.373ns.
--------------------------------------------------------------------------------
Slack: 4.627ns (requirement - (data path - clock path skew + uncertainty))
Source: u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP (RAM)
Destination: u_lvds/uut_tx/DATA_TO_OSERDES_REG_40 (FF)
Requirement: 10.000ns
Data Path Delay: 5.183ns (Levels of Logic = 0)
Clock Path Skew: -0.040ns (0.878 - 0.918)
Source Clock: CLK100 rising at 0.000ns
Destination Clock: CLK100 rising at 10.000ns
Clock Uncertainty: 0.150ns
Clock Uncertainty: 0.150ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.230ns
Phase Error (PE): 0.000ns
Maximum Data Path: u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP to u_lvds/uut_tx/DATA_TO_OSERDES_REG_40
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
RAMB36_X3Y29.DOPBDOPL0 Trcko_DOPBW 2.180 u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
SLICE_X12Y147.SR net (fanout=1) 2.462 u_lvds/uut_tx/DATA_TO_OSERDES<40>
SLICE_X12Y147.CLK Tsrck 0.541 ila0_data0<349>
u_lvds/uut_tx/DATA_TO_OSERDES_REG_40
--------------------------------------------------- ---------------------------
Total 5.183ns (2.721ns logic, 2.462ns route)
(52.5% logic, 47.5% route)
--------------------------------------------------------------------------------
Slack: 4.634ns (requirement - (data path - clock path skew + uncertainty))
Source: u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP (RAM)
Destination: u_lvds/uut_tx/DATA_TO_OSERDES_REG_48 (FF)
Requirement: 10.000ns
Data Path Delay: 5.187ns (Levels of Logic = 0)
Clock Path Skew: -0.029ns (0.878 - 0.907)
Source Clock: CLK100 rising at 0.000ns
Destination Clock: CLK100 rising at 10.000ns
Clock Uncertainty: 0.150ns
Clock Uncertainty: 0.150ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.230ns
Phase Error (PE): 0.000ns
Maximum Data Path: u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP to u_lvds/uut_tx/DATA_TO_OSERDES_REG_48
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB36_X3Y29.DOBDOU7 Trcko_DOWB 2.180 u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
SLICE_X13Y147.SR net (fanout=1) 2.462 u_lvds/uut_tx/DATA_TO_OSERDES<48>
SLICE_X13Y147.CLK Tsrck 0.545 ila0_data0<357>
u_lvds/uut_tx/DATA_TO_OSERDES_REG_48
------------------------------------------------- ---------------------------
Total 5.187ns (2.725ns logic, 2.462ns route)
(52.5% logic, 47.5% route)
--------------------------------------------------------------------------------
Slack: 4.812ns (requirement - (data path - clock path skew + uncertainty))
Source: u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP (RAM)
Destination: u_lvds/uut_tx/DATA_TO_OSERDES_REG_31 (FF)
Requirement: 10.000ns
Data Path Delay: 5.034ns (Levels of Logic = 0)
Clock Path Skew: -0.004ns (0.930 - 0.934)
Source Clock: CLK100 rising at 0.000ns
Destination Clock: CLK100 rising at 10.000ns
Clock Uncertainty: 0.150ns
Clock Uncertainty: 0.150ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.230ns
Phase Error (PE): 0.000ns
Maximum Data Path: u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP to u_lvds/uut_tx/DATA_TO_OSERDES_REG_31
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB36_X3Y28.DOBDOL15Trcko_DOWB 2.180 u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP
SLICE_X14Y144.SR net (fanout=1) 2.309 u_lvds/uut_tx/DATA_TO_OSERDES<31>
SLICE_X14Y144.CLK Tsrck 0.545 ila0_data0<340>
u_lvds/uut_tx/DATA_TO_OSERDES_REG_31
------------------------------------------------- ---------------------------
Total 5.034ns (2.725ns logic, 2.309ns route)
(54.1% logic, 45.9% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_CLK_DELAY = PERIOD TIMEGRP "CLK_DELAY" 5 ns HIGH 50%;
4099 paths analyzed, 2546 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 4.930ns.
--------------------------------------------------------------------------------
Slack: 0.070ns (requirement - (data path - clock path skew + uncertainty))
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