lvds_tx_rx_merge.vhd

FPGA之间的LVDS传输

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:45:04 08/20/2008 
-- Design Name: 
-- Module Name:    lvds_tx_rx_merge - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY lvds_tx_rx_merge IS
--	generic(
--		BLIND_MODE: INTEGER := 1
--	)
   PORT (
------------------------------------------------------------------------------------
--		din: OUT std_logic_VECTOR(63 downto 0);
--		rd_en: OUT std_logic;
--		wr_en: OUT std_logic;
--		almost_empty: OUT std_logic;
--		almost_full: OUT std_logic;
--		dout: OUT std_logic_VECTOR(63 downto 0);
--		empty: OUT std_logic;
--		full: OUT std_logic;
------------------------------------------------------------------------------------
		DATA_RX_P   : IN std_logic_vector(16 DOWNTO 0); -- SERIAL SIDE RX DATA (P)
      DATA_RX_N   : IN std_logic_vector(16 DOWNTO 0); -- SERIAL SIDE RX DATA (N)
      CLOCK_RX_P  : IN std_logic;   -- FORWARDED CLOCK FROM TX (P)
      CLOCK_RX_N  : IN std_logic;   -- FORWARDED CLOCK FROM TX (N)
      INC_PAD     : IN std_logic;   -- MANUAL INCREMENT TO DATA DELAY
      DEC_PAD     : IN std_logic;   -- MANUAL DECREMENT TO DATA DELAY
      DATA_RX_FIFO       : OUT std_logic_vector(31 DOWNTO 0);   
      DATA_RX_FIFO_VLD    : OUT std_logic;
      RESET           : IN std_logic;   -- RX DOMAIN RESET
      IDLY_RESET        : IN std_logic;   -- IDELAY TAP RESET
      IDELAYCTRL_RESET  : IN std_logic;   -- IDELAYCTRL CIRCUIT RESET
      BITSLIP_PAD       : IN std_logic;   -- MANUAL BITSLIP TO DATA
      CLK200            : IN std_logic; -- 200 MHZ REFERENCE CLOCK TO IDELAYCTRL				
      TAP_00     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_01     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_02     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_03     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_04     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_05     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_06     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_07     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_08     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_09     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_10     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_11     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_12     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_13     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_14     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_15     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_16     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_CLK    : OUT std_logic_vector(5 DOWNTO 0); 
      TRAINING_DONE_RX  : OUT std_logic;   -- ALIGNMENT OF ALL CHANNELS COMPLETE
      RXCLK          : OUT std_logic;   
      CLK_USR       : IN std_logic;   
		RXCLKDIV       : OUT std_logic;
      IDELAY_READY   : OUT std_logic;   
      RT_MANUAL_DISABLE       : IN std_logic; 
		--RX
		---------------------------------------------------------------------------
      --TX
		DATA_TX_P               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (P)
      DATA_TX_N               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (N)
      CLOCK_TX_P              : OUT std_logic;   -- FORWARDED CLOCK TO RX (P)
      CLOCK_TX_N              : OUT std_logic;   -- FORWARDED CLOCK TO RX (N)
      TXCLK                   : IN std_logic;   -- SERIAL SIDE TX CLOCK
      TXCLKDIV                : IN std_logic;   -- PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
      DATA_TX_FIFO	         : IN std_logic_vector(31 DOWNTO 0);   -- PARALLEL SIDE TX DATA
      DATA_TX_FIFO_VLD	      : IN std_logic;
      DATA_TX_FIFO_RDY	      : OUT std_logic;
      --RESET                   : IN std_logic;   -- TX DOMAIN RESET
      TRAINING_DONE_TX           : IN std_logic);   -- FLAG FROM RECEIVER INDICATING ALIGNMENT
END lvds_tx_rx_merge;

ARCHITECTURE translated OF lvds_tx_rx_merge IS
	COMPONENT DDR_6TO1_16CHAN_RT_RX
    PORT(
         DATA_RX_P : IN  std_logic_vector(16 downto 0);
         DATA_RX_N : IN  std_logic_vector(16 downto 0);
         CLOCK_RX_P : IN  std_logic;
         CLOCK_RX_N : IN  std_logic;
         INC_PAD : IN  std_logic;
         DEC_PAD : IN  std_logic;
         DATA_RX_FIFO       : OUT std_logic_vector(31 DOWNTO 0);   
			DATA_RX_FIFO_VLD    : OUT std_logic;
         RESET : IN  std_logic;
         IDLY_RESET : IN  std_logic;
         IDELAYCTRL_RESET : IN  std_logic;
         BITSLIP_PAD : IN  std_logic;
         CLK200 : IN  std_logic;
         TAP_00 : OUT  std_logic_vector(5 downto 0);
         TAP_01 : OUT  std_logic_vector(5 downto 0);
         TAP_02 : OUT  std_logic_vector(5 downto 0);
         TAP_03 : OUT  std_logic_vector(5 downto 0);
         TAP_04 : OUT  std_logic_vector(5 downto 0);
         TAP_05 : OUT  std_logic_vector(5 downto 0);
         TAP_06 : OUT  std_logic_vector(5 downto 0);
         TAP_07 : OUT  std_logic_vector(5 downto 0);
         TAP_08 : OUT  std_logic_vector(5 downto 0);
         TAP_09 : OUT  std_logic_vector(5 downto 0);
         TAP_10 : OUT  std_logic_vector(5 downto 0);
         TAP_11 : OUT  std_logic_vector(5 downto 0);
         TAP_12 : OUT  std_logic_vector(5 downto 0);
         TAP_13 : OUT  std_logic_vector(5 downto 0);
         TAP_14 : OUT  std_logic_vector(5 downto 0);
         TAP_15 : OUT  std_logic_vector(5 downto 0);
         TAP_16 : OUT  std_logic_vector(5 downto 0);
         TAP_CLK : OUT  std_logic_vector(5 downto 0);
         TRAINING_DONE : OUT  std_logic;
         RXCLK : OUT  std_logic;
         RXCLK_USR : IN  std_logic;
			RXCLKDIV       : OUT std_logic;
         IDELAY_READY : OUT  std_logic;
         RT_MANUAL_DISABLE : IN  std_logic
        );
    END COMPONENT;
    
	 COMPONENT DDR_6TO1_16CHAN_RT_TX
    PORT(
	 ------------------------------------------------
--	 		din: OUT std_logic_VECTOR(63 downto 0);
--		rd_en: OUT std_logic;
--		wr_en: OUT std_logic;
--		almost_empty: OUT std_logic;
--		almost_full: OUT std_logic;
--		dout: OUT std_logic_VECTOR(63 downto 0);
--		empty: OUT std_logic;
--		full: OUT std_logic;
		----------------------------------------------------
         DATA_TX_P : OUT  std_logic_vector(16 downto 0);
         DATA_TX_N : OUT  std_logic_vector(16 downto 0);
         CLOCK_TX_P : OUT  std_logic;
         CLOCK_TX_N : OUT  std_logic;
         TXCLK : IN  std_logic;
         TXCLKDIV : IN  std_logic;
         DATA_TX_FIFO	         : IN std_logic_vector(31 DOWNTO 0);   -- PARALLEL SIDE TX DATA
			DATA_TX_FIFO_VLD	      : IN std_logic;
			DATA_TX_FIFO_RDY	      : OUT std_logic;
			TXCLK_USR					: IN std_logic;
         RESET : IN  std_logic;
         TRAINING_DONE : IN  std_logic
        );
    END COMPONENT;

BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut_rx: DDR_6TO1_16CHAN_RT_RX PORT MAP (
          DATA_RX_P => DATA_RX_P,
          DATA_RX_N => DATA_RX_N,
          CLOCK_RX_P => CLOCK_RX_P,
          CLOCK_RX_N => CLOCK_RX_N,
          INC_PAD => INC_PAD,
          DEC_PAD => DEC_PAD,
          DATA_RX_FIFO      => DATA_RX_FIFO,   
			 DATA_RX_FIFO_VLD  => DATA_RX_FIFO_VLD,
          RESET => RESET,
          IDLY_RESET => IDLY_RESET,
          IDELAYCTRL_RESET => IDELAYCTRL_RESET,
          BITSLIP_PAD => BITSLIP_PAD,
          CLK200 => CLK200,
          TAP_00 => TAP_00,
          TAP_01 => TAP_01,
          TAP_02 => TAP_02,
          TAP_03 => TAP_03,
          TAP_04 => TAP_04,
          TAP_05 => TAP_05,
          TAP_06 => TAP_06,
          TAP_07 => TAP_07,
          TAP_08 => TAP_08,
          TAP_09 => TAP_09,
          TAP_10 => TAP_10,
          TAP_11 => TAP_11,
          TAP_12 => TAP_12,
          TAP_13 => TAP_13,
          TAP_14 => TAP_14,
          TAP_15 => TAP_15,
          TAP_16 => TAP_16,
          TAP_CLK => TAP_CLK,
          TRAINING_DONE => TRAINING_DONE_RX,
          RXCLK => RXCLK,
          RXCLK_USR => CLK_USR,
          RXCLKDIV => RXCLKDIV,
          IDELAY_READY => IDELAY_READY,
          RT_MANUAL_DISABLE => RT_MANUAL_DISABLE
        );
 
	-- Instantiate the Unit Under Test (UUT)
   uut_tx: DDR_6TO1_16CHAN_RT_TX PORT MAP (
	----------------------------------------------------------------------
--			din				 => din,
--			rd_en				 => rd_en,
--			wr_en				 => wr_en,
--			almost_empty	 => almost_empty,
--			almost_full		 => almost_full,
--			dout				 => dout,
--			empty				 => empty,
--			full				 => full,
	----------------------------------------------------------------------
          DATA_TX_P => DATA_TX_P,
          DATA_TX_N => DATA_TX_N,
          CLOCK_TX_P => CLOCK_TX_P,
          CLOCK_TX_N => CLOCK_TX_N,
          TXCLK => TXCLK,
          TXCLKDIV => TXCLKDIV,
          DATA_TX_FIFO	      =>  DATA_TX_FIFO, 
			 DATA_TX_FIFO_VLD	   =>  DATA_TX_FIFO_VLD,
			 DATA_TX_FIFO_RDY	   =>  DATA_TX_FIFO_RDY,
			 TXCLK_USR => CLK_USR,
          RESET => RESET,
          TRAINING_DONE => TRAINING_DONE_TX
        );
END;