uut_tx_wrapper_map.mrp

FPGA之间的LVDS传输

Release 10.1.02 Map K.37 (nt)
Xilinx Mapping Report File for Design 'uut_tx_wrapper'

Design Information
------------------
Command Line   : map -ise E:/ISEworks/LVDS/LVDS-func/xapp860.ise -intstyle ise
-p xc5vsx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -cm area -pr off -k 6 -lc
off -power off -o uut_tx_wrapper_map.ncd uut_tx_wrapper.ngd uut_tx_wrapper.pcf 
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Wed Aug 20 15:31:21 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:   17
Slice Logic Utilization:
  Number of Slice Registers:                    96 out of  32,640    1%
    Number used as Flip Flops:                  96
  Number of Slice LUTs:                         48 out of  32,640    1%
    Number used as logic:                       48 out of  32,640    1%
      Number using O6 output only:              48

Slice Logic Distribution:
  Number of occupied Slices:                    71 out of   8,160    1%
  Number of LUT Flip Flop pairs used:           96
    Number with an unused Flip Flop:             0 out of      96    0%
    Number with an unused LUT:                  48 out of      96   50%
    Number of fully used LUT-FF pairs:          48 out of      96   50%
    Number of unique control sets:              49
    Number of slice register sites lost
      to control set restrictions:             144 out of  32,640    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       134 out of     480   27%
    IOB Flip Flops:                              1
    IOB Master Pads:                            17
    IOB Slave Pads:                             17

Specific Feature Utilization:
  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%
    Number used as BUFGs:                        2
  Number of OSERDESs:                           16

Peak Memory Usage:  365 MB
Total REAL time to MAP completion:  30 secs 
Total CPU time to MAP completion:   24 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_00 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_01 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_02 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_10 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_03 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_11 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_04 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_12 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_05 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_13 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_06 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_14 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_07 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_15 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_08 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   uutt/OSERDES_TX_DATA_09 with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects
   TRISTATE_WIDTH to be set 4. 

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
   1.050 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |             | Strength | Rate |              |          | Delay    |
+----------------------------------------------------------------------------------------------------------------------------------------+
| CLOCK_TX_N                         | IOBS             | OUTPUT    | See master  |          |      |              |          |          |
| CLOCK_TX_P                         | IOBM             | OUTPUT    | LVDSEXT_25  |          |      | ODDR         |          |          |
| DATA_TO_OSERDES<0>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<1>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<2>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<3>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<4>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<5>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<6>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<7>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<8>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<9>                 | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<10>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<11>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<12>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<13>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<14>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<15>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<16>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| DATA_TO_OSERDES<17>                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |