lvds_tx_rx_merge.twr

FPGA之间的LVDS传输

  Clock Path Skew:      -0.261ns (1.442 - 1.703)
  Source Clock:         CLK_USR_BUFGP rising at 0.000ns
  Destination Clock:    CLK_USR_BUFGP rising at 6.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP to uut_rx/DATA_RX_FIFO_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y7.DOADOU5  Trcko_DO              2.180   uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
                                                       uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
    OLOGIC_X0Y150.D1     net (fanout=1)        2.817   uut_rx/dout<11>
    OLOGIC_X0Y150.CLK    Todck                 0.434   uut_rx/DATA_RX_FIFO<11>
                                                       uut_rx/DATA_RX_FIFO_11
    -------------------------------------------------  ---------------------------
    Total                                      5.431ns (2.614ns logic, 2.817ns route)
                                                       (48.1% logic, 51.9% route)

--------------------------------------------------------------------------------
Slack:                  0.390ns (requirement - (data path - clock path skew + uncertainty))
  Source:               uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (RAM)
  Destination:          uut_rx/DATA_RX_FIFO_21 (FF)
  Requirement:          6.000ns
  Data Path Delay:      5.209ns (Levels of Logic = 0)
  Clock Path Skew:      -0.366ns (1.337 - 1.703)
  Source Clock:         CLK_USR_BUFGP rising at 0.000ns
  Destination Clock:    CLK_USR_BUFGP rising at 6.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP to uut_rx/DATA_RX_FIFO_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y7.DOADOU10 Trcko_DO              2.180   uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
                                                       uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
    OLOGIC_X2Y66.D1      net (fanout=1)        2.595   uut_rx/dout<21>
    OLOGIC_X2Y66.CLK     Todck                 0.434   uut_rx/DATA_RX_FIFO<21>
                                                       uut_rx/DATA_RX_FIFO_21
    -------------------------------------------------  ---------------------------
    Total                                      5.209ns (2.614ns logic, 2.595ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack:                  0.405ns (requirement - (data path - clock path skew + uncertainty))
  Source:               uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (RAM)
  Destination:          uut_rx/DATA_RX_FIFO_49 (FF)
  Requirement:          6.000ns
  Data Path Delay:      5.187ns (Levels of Logic = 0)
  Clock Path Skew:      -0.373ns (1.330 - 1.703)
  Source Clock:         CLK_USR_BUFGP rising at 0.000ns
  Destination Clock:    CLK_USR_BUFGP rising at 6.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP to uut_rx/DATA_RX_FIFO_49
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB36_X0Y7.DOBDOU8  Trcko_DO              2.180   uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
                                                       uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
    OLOGIC_X2Y61.D1      net (fanout=1)        2.573   uut_rx/dout<49>
    OLOGIC_X2Y61.CLK     Todck                 0.434   uut_rx/DATA_RX_FIFO<49>
                                                       uut_rx/DATA_RX_FIFO_49
    -------------------------------------------------  ---------------------------
    Total                                      5.187ns (2.614ns logic, 2.573ns route)
                                                       (50.4% logic, 49.6% route)

--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK_USR
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_USR        |    5.727|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock TXCLKDIV
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
TXCLKDIV       |    5.284|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 755 paths, 0 nets, and 873 connections

Design statistics:
   Minimum period:   5.727ns{1}   (Maximum frequency: 174.611MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Mon Aug 25 17:19:32 2008 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 260 MB