📄 lvds_tx_rx_merge.twr
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Release 10.1.02 Trace (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
K:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/ISEworks/LVDS/LVDS_4to1/xapp860.ise -intstyle ise -v 3 -s 1 -xml
lvds_tx_rx_merge lvds_tx_rx_merge.ncd -o lvds_tx_rx_merge.twr
lvds_tx_rx_merge.pcf -ucf lvds_tx_rx_merge.ucf
Design file: lvds_tx_rx_merge.ncd
Physical constraint file: lvds_tx_rx_merge.pcf
Device,package,speed: xc5vsx50t,ff1136,-1 (PRODUCTION 1.61 2008-05-28, STEPPING level 0)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_TXCLKDIV = PERIOD TIMEGRP "TXCLKDIV" 6 ns HIGH 50%;
319 paths analyzed, 257 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.284ns.
--------------------------------------------------------------------------------
Slack: 0.716ns (requirement - (data path - clock path skew + uncertainty))
Source: uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (RAM)
Destination: uut_tx/DATA_TO_OSERDES_REG_35 (FF)
Requirement: 6.000ns
Data Path Delay: 5.046ns (Levels of Logic = 0)
Clock Path Skew: -0.203ns (1.215 - 1.418)
Source Clock: TXCLKDIV_BUFGP rising at 0.000ns
Destination Clock: TXCLKDIV_BUFGP rising at 6.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP to uut_tx/DATA_TO_OSERDES_REG_35
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB36_X4Y15.DOADOU15Trcko_DO 2.180 uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
SLICE_X55Y43.SR net (fanout=1) 2.321 uut_tx/DATA_TO_OSERDES<31>
SLICE_X55Y43.CLK Tsrck 0.545 uut_tx/DATA_TO_OSERDES_REG<35>
uut_tx/DATA_TO_OSERDES_REG_35
------------------------------------------------- ---------------------------
Total 5.046ns (2.725ns logic, 2.321ns route)
(54.0% logic, 46.0% route)
--------------------------------------------------------------------------------
Slack: 0.883ns (requirement - (data path - clock path skew + uncertainty))
Source: uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (RAM)
Destination: uut_tx/DATA_TO_OSERDES_REG_32 (FF)
Requirement: 6.000ns
Data Path Delay: 4.906ns (Levels of Logic = 0)
Clock Path Skew: -0.176ns (1.237 - 1.413)
Source Clock: TXCLKDIV_BUFGP rising at 0.000ns
Destination Clock: TXCLKDIV_BUFGP rising at 6.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP to uut_tx/DATA_TO_OSERDES_REG_32
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB36_X4Y15.DOADOL14Trcko_DO 2.180 uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
SLICE_X54Y44.SR net (fanout=1) 2.179 uut_tx/DATA_TO_OSERDES<28>
SLICE_X54Y44.CLK Tsrck 0.547 uut_tx/DATA_TO_OSERDES_REG<32>
uut_tx/DATA_TO_OSERDES_REG_32
------------------------------------------------- ---------------------------
Total 4.906ns (2.727ns logic, 2.179ns route)
(55.6% logic, 44.4% route)
--------------------------------------------------------------------------------
Slack: 0.938ns (requirement - (data path - clock path skew + uncertainty))
Source: uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (RAM)
Destination: uut_tx/DATA_TO_OSERDES_REG_33 (FF)
Requirement: 6.000ns
Data Path Delay: 4.849ns (Levels of Logic = 1)
Clock Path Skew: -0.178ns (1.240 - 1.418)
Source Clock: TXCLKDIV_BUFGP rising at 0.000ns
Destination Clock: TXCLKDIV_BUFGP rising at 6.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path: uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP to uut_tx/DATA_TO_OSERDES_REG_33
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB36_X4Y15.DOADOU14Trcko_DO 2.180 uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
SLICE_X54Y43.A2 net (fanout=1) 2.643 uut_tx/DATA_TO_OSERDES<29>
SLICE_X54Y43.CLK Tas 0.026 uut_tx/DATA_TO_OSERDES_REG<34>
uut_tx/DATA_TO_OSERDES_REG_mux0002<33>11
uut_tx/DATA_TO_OSERDES_REG_33
------------------------------------------------- ---------------------------
Total 4.849ns (2.206ns logic, 2.643ns route)
(45.5% logic, 54.5% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_CLK_USR = PERIOD TIMEGRP "CLK_USR" 6 ns HIGH 50%;
436 paths analyzed, 334 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.727ns.
--------------------------------------------------------------------------------
Slack: 0.273ns (requirement - (data path - clock path skew + uncertainty))
Source: uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (RAM)
Destination: uut_rx/DATA_RX_FIFO_11 (FF)
Requirement: 6.000ns
Data Path Delay: 5.431ns (Levels of Logic = 0)
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