lvds_tx_rx_merge_map.map

FPGA之间的LVDS传输

Release 10.1.02 Map K.37 (nt)
Xilinx Map Application Log File for Design 'lvds_tx_rx_merge'

Design Information
------------------
Command Line   : map -ise E:/ISEworks/LVDS/LVDS_4to1/xapp860.ise -intstyle ise
-p xc5vsx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -cm area -pr o -k 6 -lc
off -power off -o lvds_tx_rx_merge_map.ncd lvds_tx_rx_merge.ngd
lvds_tx_rx_merge.pcf 
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Mon Aug 25 17:16:54 2008

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:3b9f57) REAL time: 12 secs 

Phase 2.7
Phase 2.7 (Checksum:3b9f57) REAL time: 14 secs 

Phase 3.31
Phase 3.31 (Checksum:47b1df) REAL time: 14 secs 

Phase 4.33
Phase 4.33 (Checksum:47b1df) REAL time: 20 secs 

Phase 5.32
Phase 5.32 (Checksum:47b1df) REAL time: 21 secs 

Phase 6.2
....
...........................


There are 12 clock regions on the target FPGA device:
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y5:                        | CLOCKREGION_X1Y5:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
|   0 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   4 Regional Clock Spines, 1 in use      |   4 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |
|   2 BUFRs available, 1 in use            |   2 BUFRs available, 0 in use            |
|   4 Regional Clock Spines, 1 in use      |   4 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 1 in use      |   4 edge BUFIOs available, 0 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   4 Regional Clock Spines, 1 in use      |   4 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
|   0 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|


Clock-Region: <CLOCKREGION_X0Y1>
  key resource utilizations (used/available): edge-bufios - 1/4; center-bufios - 0/2; bufrs - 1/2; regional-clock-spines - 1/4
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|       | Upper Region|  12  |  0  |  0 |   60   |   60   |  2880 |  2400 |  3360 |  32  |   0  |  0  |   0  | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|       |CurrentRegion|  12  |  2  |  0 |   60   |   60   |  2880 |  2400 |  3360 |  32  |   0  |  0  |   0  | <- Available resources in the current region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|       | Lower Region|  12  |  4  |  0 |   40   |   40   |  2880 |  2400 |  3360 |  32  |   0  |  0  |   0  | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| clock |    region   |                                                                                      -----------------------------------------------
|  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| BUFIO |             |   0  |  0  |  0 |   34   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "uut_rx/RXCLK_TEMP"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|  BUFR | Upper/Lower |   1  |  0  |  0 |   34   |    0   |   128 |     4 |   318 |   0  |   0  |  0  |   0  | "RXCLKDIV_OBUF"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------




######################################################################################
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
#
# Number of Regional Clocking Regions in the device: 12  (4 clock spines in each)
# Number of Regional Clock Networks used in this design: 2 (each network can be
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
# 
######################################################################################

# IO-Clock "uut_rx/RXCLK_TEMP" driven by "BUFIO_X0Y5"
INST "uut_rx/RX_CLK_BUFIO" LOC = "BUFIO_X0Y5" ;
NET "uut_rx/RXCLK_TEMP" TNM_NET = "TN_uut_rx/RXCLK_TEMP" ;
TIMEGRP "TN_uut_rx/RXCLK_TEMP" AREA_GROUP = "CLKAG_uut_rx/RXCLK_TEMP" ;
AREA_GROUP "CLKAG_uut_rx/RXCLK_TEMP" RANGE = CLOCKREGION_X0Y1;


# Regional-Clock "RXCLKDIV_OBUF" driven by "BUFR_X0Y3"
INST "uut_rx/RX_CLK_BUFR" LOC = "BUFR_X0Y3" ;
NET "RXCLKDIV_OBUF" TNM_NET = "TN_RXCLKDIV_OBUF" ;
TIMEGRP "TN_RXCLKDIV_OBUF" AREA_GROUP = "CLKAG_RXCLKDIV_OBUF" ;
AREA_GROUP "CLKAG_RXCLKDIV_OBUF" RANGE = CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y0;


.
Phase 6.2 (Checksum:502aee) REAL time: 29 secs 

Phase 7.30
Phase 7.30 (Checksum:502aee) REAL time: 29 secs 

Phase 8.3
...
Phase 8.3 (Checksum:165400d) REAL time: 33 secs 

Phase 9.5
Phase 9.5 (Checksum:165400d) REAL time: 33 secs 

Phase 10.8
............................
.....................
.....................
Phase 10.8 (Checksum:4f9578d) REAL time: 35 secs 

Phase 11.29
Phase 11.29 (Checksum:4f9578d) REAL time: 35 secs 

Phase 12.5
Phase 12.5 (Checksum:4f9578d) REAL time: 35 secs 

Phase 13.18
Phase 13.18 (Checksum:4f07194) REAL time: 53 secs 

Phase 14.5
Phase 14.5 (Checksum:4f07194) REAL time: 53 secs 

Phase 15.34
Phase 15.34 (Checksum:4f07194) REAL time: 53 secs 

REAL time consumed by placer: 54 secs 
CPU  time consumed by placer: 50 secs 

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   89
Slice Logic Utilization:
  Number of Slice Registers:                   675 out of  32,640    2%
    Number used as Flip Flops:                 675
  Number of Slice LUTs:                        811 out of  32,640    2%
    Number used as logic:                      806 out of  32,640    2%
      Number using O6 output only:             806
    Number used as Memory:                       5 out of  12,480    1%
      Number used as Shift Register:             5
        Number using O6 output only:             5

Slice Logic Distribution:
  Number of occupied Slices:                   421 out of   8,160    5%
  Number of LUT Flip Flop pairs used:        1,048
    Number with an unused Flip Flop:           373 out of   1,048   35%
    Number with an unused LUT:                 237 out of   1,048   22%
    Number of fully used LUT-FF pairs:         438 out of   1,048   41%
    Number of unique control sets:              88
    Number of slice register sites lost
      to control set restrictions:             216 out of  32,640    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       327 out of     480   68%
    IOB Flip Flops:                             67
    IOB Master Pads:                            18
    IOB Slave Pads:                             18

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                       2 out of     132    1%
    Number using BlockRAM only:                  2
    Total primitives used:
      Number of 36k BlockRAM used:               2
    Total Memory used (KB):                     72 out of   4,752    1%
  Number of BUFG/BUFGCTRLs:                      4 out of      32   12%
    Number used as BUFGs:                        4
  Number of BUFIOs:                              1 out of      56    1%
  Number of BUFRs:                               1 out of      24    4%
  Number of ISERDESs:                           34
  Number of OSERDESs:                           17

Peak Memory Usage:  398 MB
Total REAL time to MAP completion:  1 mins 15 secs 
Total CPU time to MAP completion:   1 mins 9 secs 

Mapping completed.
See MAP report file "lvds_tx_rx_merge_map.mrp" for details.