lvds_bist_top.twx

来自「FPGA之间的LVDS传输」· TWX 代码 · 共 341 行 · 第 1/3 页

<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 10.1.02 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle
ise -v 3 -s 1 -xml lvds_bist_top lvds_bist_top.ncd -o lvds_bist_top.twr
lvds_bist_top.pcf -ucf lvds_tx_rx_merge.ucf

</twCmdLine><twDesign>lvds_bist_top.ncd</twDesign><twPCF>lvds_bist_top.pcf</twPCF><twDevInfo arch="virtex5" pkg="ff1738"><twDevName>xc5vfx130t</twDevName><twSpeedGrade>-1</twSpeedGrade><twSpeedVer>ADVANCED 1.61 2008-05-28, STEPPING level 0</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo>INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst twConstType="PERIOD" ><twConstHead uID="0B6E72B8"><twConstName UCFConstName="">TS_CLK100 = PERIOD TIMEGRP &quot;CLK100&quot; 10 ns HIGH 50%;</twConstName><twItemCnt>348</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>282</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.373</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>4.627</twSlack><twSrc BELType="RAM">u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twSrc><twDest BELType="FF">u_lvds/uut_tx/DATA_TO_OSERDES_REG_40</twDest><twTotPathDel>5.183</twTotPathDel><twClkSkew dest = "0.878" src = "0.918">0.040</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.230" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.150</twClkUncert><twDetPath maxSiteLen="22"><twSrc BELType='RAM'>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twSrc><twDest BELType='FF'>u_lvds/uut_tx/DATA_TO_OSERDES_REG_40</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X3Y29.CLKBWRCLKL</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK100</twSrcClk><twPathDel><twSite>RAMB36_X3Y29.DOPBDOPL0</twSite><twDelType>Trcko_DOPBW</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twComp><twBEL>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twBEL></twPathDel><twPathDel><twSite>SLICE_X12Y147.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.462</twDelInfo><twComp>u_lvds/uut_tx/DATA_TO_OSERDES&lt;40&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X12Y147.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twRising">0.541</twDelInfo><twComp>ila0_data0&lt;349&gt;</twComp><twBEL>u_lvds/uut_tx/DATA_TO_OSERDES_REG_40</twBEL></twPathDel><twLogDel>2.721</twLogDel><twRouteDel>2.462</twRouteDel><twTotDel>5.183</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CLK100</twDestClk><twPctLog>52.5</twPctLog><twPctRoute>47.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>4.634</twSlack><twSrc BELType="RAM">u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twSrc><twDest BELType="FF">u_lvds/uut_tx/DATA_TO_OSERDES_REG_48</twDest><twTotPathDel>5.187</twTotPathDel><twClkSkew dest = "0.878" src = "0.907">0.029</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.230" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.150</twClkUncert><twDetPath maxSiteLen="20"><twSrc BELType='RAM'>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twSrc><twDest BELType='FF'>u_lvds/uut_tx/DATA_TO_OSERDES_REG_48</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X3Y29.CLKBWRCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK100</twSrcClk><twPathDel><twSite>RAMB36_X3Y29.DOBDOU7</twSite><twDelType>Trcko_DOWB</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twComp><twBEL>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twBEL></twPathDel><twPathDel><twSite>SLICE_X13Y147.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.462</twDelInfo><twComp>u_lvds/uut_tx/DATA_TO_OSERDES&lt;48&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X13Y147.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twRising">0.545</twDelInfo><twComp>ila0_data0&lt;357&gt;</twComp><twBEL>u_lvds/uut_tx/DATA_TO_OSERDES_REG_48</twBEL></twPathDel><twLogDel>2.725</twLogDel><twRouteDel>2.462</twRouteDel><twTotDel>5.187</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CLK100</twDestClk><twPctLog>52.5</twPctLog><twPctRoute>47.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>4.812</twSlack><twSrc BELType="RAM">u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twSrc><twDest BELType="FF">u_lvds/uut_tx/DATA_TO_OSERDES_REG_31</twDest><twTotPathDel>5.034</twTotPathDel><twClkSkew dest = "0.930" src = "0.934">0.004</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.230" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.150</twClkUncert><twDetPath maxSiteLen="21"><twSrc BELType='RAM'>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twSrc><twDest BELType='FF'>u_lvds/uut_tx/DATA_TO_OSERDES_REG_31</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X3Y28.CLKBWRCLKL</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK100</twSrcClk><twPathDel><twSite>RAMB36_X3Y28.DOBDOL15</twSite><twDelType>Trcko_DOWB</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twComp><twBEL>u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP</twBEL></twPathDel><twPathDel><twSite>SLICE_X14Y144.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.309</twDelInfo><twComp>u_lvds/uut_tx/DATA_TO_OSERDES&lt;31&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X14Y144.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twRising">0.545</twDelInfo><twComp>ila0_data0&lt;340&gt;</twComp><twBEL>u_lvds/uut_tx/DATA_TO_OSERDES_REG_31</twBEL></twPathDel><twLogDel>2.725</twLogDel><twRouteDel>2.309</twRouteDel><twTotDel>5.034</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">CLK100</twDestClk><twPctLog>54.1</twPctLog><twPctRoute>45.9</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twConst twConstType="PERIOD" ><twConstHead uID="0B6E71A0"><twConstName UCFConstName="">TS_CLK_DELAY = PERIOD TIMEGRP &quot;CLK_DELAY&quot; 5 ns HIGH 50%;</twConstName><twItemCnt>4099</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>2546</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.930</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.070</twSlack><twSrc BELType="FF">U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twSrc><twDest BELType="RAM">U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twDest><twTotPathDel>4.694</twTotPathDel><twClkSkew dest = "1.371" src = "1.502">0.131</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.140" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="23"><twSrc BELType='FF'>U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twSrc><twDest BELType='RAM'>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X45Y104.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_DELAY</twSrcClk><twPathDel><twSite>SLICE_X45Y104.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR&lt;10&gt;</twComp><twBEL>U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twBEL></twPathDel><twPathDel><twSite>RAMB36_X6Y21.ADDRBU13</twSite><twDelType>net</twDelType><twFanCnt>43</twFanCnt><twDelInfo twEdge="twRising">3.897</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>RAMB36_X6Y21.CLKBWRCLKU</twSite><twDelType>Trcck_ADDRB</twDelType><twDelInfo twEdge="twRising">0.347</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twComp><twBEL>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twBEL></twPathDel><twLogDel>0.797</twLogDel><twRouteDel>3.897</twRouteDel><twTotDel>4.694</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">CLK_DELAY</twDestClk><twPctLog>17.0</twPctLog><twPctRoute>83.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.081</twSlack><twSrc BELType="FF">U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twSrc><twDest BELType="RAM">U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twDest><twTotPathDel>4.694</twTotPathDel><twClkSkew dest = "1.382" src = "1.502">0.120</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.140" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="23"><twSrc BELType='FF'>U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twSrc><twDest BELType='RAM'>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X45Y104.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_DELAY</twSrcClk><twPathDel><twSite>SLICE_X45Y104.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR&lt;10&gt;</twComp><twBEL>U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twBEL></twPathDel><twPathDel><twSite>RAMB36_X6Y21.ADDRBL13</twSite><twDelType>net</twDelType><twFanCnt>43</twFanCnt><twDelInfo twEdge="twRising">3.897</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>RAMB36_X6Y21.CLKBWRCLKL</twSite><twDelType>Trcck_ADDRB</twDelType><twDelInfo twEdge="twRising">0.347</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twComp><twBEL>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36</twBEL></twPathDel><twLogDel>0.797</twLogDel><twRouteDel>3.897</twRouteDel><twTotDel>4.694</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">CLK_DELAY</twDestClk><twPctLog>17.0</twPctLog><twPctRoute>83.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.091</twSlack><twSrc BELType="FF">U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twSrc><twDest BELType="RAM">U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36</twDest><twTotPathDel>4.584</twTotPathDel><twClkSkew dest = "1.282" src = "1.502">0.220</twClkSkew><twDelConst>5.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.140" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.105</twClkUncert><twDetPath maxSiteLen="23"><twSrc BELType='FF'>U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twSrc><twDest BELType='RAM'>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X45Y104.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_DELAY</twSrcClk><twPathDel><twSite>SLICE_X45Y104.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR&lt;10&gt;</twComp><twBEL>U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[9].U_CAP_ADDR</twBEL></twPathDel><twPathDel><twSite>RAMB36_X5Y19.ADDRBL13</twSite><twDelType>net</twDelType><twFanCnt>43</twFanCnt><twDelInfo twEdge="twRising">3.787</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/iCAP_WR_ADDR&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>RAMB36_X5Y19.CLKBWRCLKL</twSite><twDelType>Trcck_ADDRB</twDelType><twDelInfo twEdge="twRising">0.347</twDelInfo><twComp>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36</twComp><twBEL>U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36</twBEL></twPathDel><twLogDel>0.797</twLogDel><twRouteDel>3.787</twRouteDel><twTotDel>4.584</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="5.000">CLK_DELAY</twDestClk><twPctLog>17.4</twPctLog><twPctRoute>82.6</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twUnmetConstCnt>0</twUnmetConstCnt><twDataSheet twNameLen="15"><twClk2SUList twDestWidth = "7"><twDest>CLK_50M</twDest><twClk2SU><twSrc>CLK_50M</twSrc><twRiseRise>5.373</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum><twErrCnt>0</twErrCnt><twScore>0</twScore><twConstCov><twPathCnt>4447</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>3467</twConnCnt></twConstCov><twStats><twMinPer>5.373</twMinPer><twFootnote number="1" /><twMaxFreq>186.116</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Sun Jan 11 23:20:17 2009 </twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 377 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>