lvds_tx_rx_merge.twx

FPGA之间的LVDS传输

<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 10.1.02 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>K:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/ISEworks/LVDS/LVDS_4to1/xapp860.ise -intstyle ise -v 3 -s 1 -xml
lvds_tx_rx_merge lvds_tx_rx_merge.ncd -o lvds_tx_rx_merge.twr
lvds_tx_rx_merge.pcf -ucf lvds_tx_rx_merge.ucf

</twCmdLine><twDesign>lvds_tx_rx_merge.ncd</twDesign><twPCF>lvds_tx_rx_merge.pcf</twPCF><twDevInfo arch="virtex5" pkg="ff1136"><twDevName>xc5vsx50t</twDevName><twSpeedGrade>-1</twSpeedGrade><twSpeedVer>PRODUCTION 1.61 2008-05-28, STEPPING level 0</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo>INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst twConstType="PERIOD" ><twConstHead uID="07E072B8"><twConstName UCFConstName="TIMESPEC TS_TXCLKDIV = PERIOD &quot;TXCLKDIV&quot; 6 ns HIGH 50%;">TS_TXCLKDIV = PERIOD TIMEGRP &quot;TXCLKDIV&quot; 6 ns HIGH 50%;</twConstName><twItemCnt>319</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>257</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.284</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.716</twSlack><twSrc BELType="RAM">uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType="FF">uut_tx/DATA_TO_OSERDES_REG_35</twDest><twTotPathDel>5.046</twTotPathDel><twClkSkew dest = "1.215" src = "1.418">0.203</twClkSkew><twDelConst>6.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="21"><twSrc BELType='RAM'>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType='FF'>uut_tx/DATA_TO_OSERDES_REG_35</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X4Y15.CLKARDCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">TXCLKDIV_BUFGP</twSrcClk><twPathDel><twSite>RAMB36_X4Y15.DOADOU15</twSite><twDelType>Trcko_DO</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twComp><twBEL>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twBEL></twPathDel><twPathDel><twSite>SLICE_X55Y43.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.321</twDelInfo><twComp>uut_tx/DATA_TO_OSERDES&lt;31&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X55Y43.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twRising">0.545</twDelInfo><twComp>uut_tx/DATA_TO_OSERDES_REG&lt;35&gt;</twComp><twBEL>uut_tx/DATA_TO_OSERDES_REG_35</twBEL></twPathDel><twLogDel>2.725</twLogDel><twRouteDel>2.321</twRouteDel><twTotDel>5.046</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.000">TXCLKDIV_BUFGP</twDestClk><twPctLog>54.0</twPctLog><twPctRoute>46.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.883</twSlack><twSrc BELType="RAM">uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType="FF">uut_tx/DATA_TO_OSERDES_REG_32</twDest><twTotPathDel>4.906</twTotPathDel><twClkSkew dest = "1.237" src = "1.413">0.176</twClkSkew><twDelConst>6.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="21"><twSrc BELType='RAM'>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType='FF'>uut_tx/DATA_TO_OSERDES_REG_32</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X4Y15.CLKARDCLKL</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">TXCLKDIV_BUFGP</twSrcClk><twPathDel><twSite>RAMB36_X4Y15.DOADOL14</twSite><twDelType>Trcko_DO</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twComp><twBEL>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y44.SR</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.179</twDelInfo><twComp>uut_tx/DATA_TO_OSERDES&lt;28&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y44.CLK</twSite><twDelType>Tsrck</twDelType><twDelInfo twEdge="twRising">0.547</twDelInfo><twComp>uut_tx/DATA_TO_OSERDES_REG&lt;32&gt;</twComp><twBEL>uut_tx/DATA_TO_OSERDES_REG_32</twBEL></twPathDel><twLogDel>2.727</twLogDel><twRouteDel>2.179</twRouteDel><twTotDel>4.906</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.000">TXCLKDIV_BUFGP</twDestClk><twPctLog>55.6</twPctLog><twPctRoute>44.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.938</twSlack><twSrc BELType="RAM">uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType="FF">uut_tx/DATA_TO_OSERDES_REG_33</twDest><twTotPathDel>4.849</twTotPathDel><twClkSkew dest = "1.240" src = "1.418">0.178</twClkSkew><twDelConst>6.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="21"><twSrc BELType='RAM'>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType='FF'>uut_tx/DATA_TO_OSERDES_REG_33</twDest><twLogLvls>1</twLogLvls><twSrcSite>RAMB36_X4Y15.CLKARDCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">TXCLKDIV_BUFGP</twSrcClk><twPathDel><twSite>RAMB36_X4Y15.DOADOU14</twSite><twDelType>Trcko_DO</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twComp><twBEL>uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twBEL></twPathDel><twPathDel><twSite>SLICE_X54Y43.A2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.643</twDelInfo><twComp>uut_tx/DATA_TO_OSERDES&lt;29&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X54Y43.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.026</twDelInfo><twComp>uut_tx/DATA_TO_OSERDES_REG&lt;34&gt;</twComp><twBEL>uut_tx/DATA_TO_OSERDES_REG_mux0002&lt;33&gt;11</twBEL><twBEL>uut_tx/DATA_TO_OSERDES_REG_33</twBEL></twPathDel><twLogDel>2.206</twLogDel><twRouteDel>2.643</twRouteDel><twTotDel>4.849</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.000">TXCLKDIV_BUFGP</twDestClk><twPctLog>45.5</twPctLog><twPctRoute>54.5</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twConst twConstType="PERIOD" ><twConstHead uID="07E071A0"><twConstName UCFConstName="TIMESPEC TS_CLK_USR = PERIOD &quot;CLK_USR&quot; 6 ns HIGH 50%;">TS_CLK_USR = PERIOD TIMEGRP &quot;CLK_USR&quot; 6 ns HIGH 50%;</twConstName><twItemCnt>436</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twEndPtCnt>334</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>5.727</twMinPer></twConstHead><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.273</twSlack><twSrc BELType="RAM">uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType="FF">uut_rx/DATA_RX_FIFO_11</twDest><twTotPathDel>5.431</twTotPathDel><twClkSkew dest = "1.442" src = "1.703">0.261</twClkSkew><twDelConst>6.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="19"><twSrc BELType='RAM'>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType='FF'>uut_rx/DATA_RX_FIFO_11</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X0Y7.CLKARDCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_USR_BUFGP</twSrcClk><twPathDel><twSite>RAMB36_X0Y7.DOADOU5</twSite><twDelType>Trcko_DO</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twComp><twBEL>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X0Y150.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.817</twDelInfo><twComp>uut_rx/dout&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X0Y150.CLK</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.434</twDelInfo><twComp>uut_rx/DATA_RX_FIFO&lt;11&gt;</twComp><twBEL>uut_rx/DATA_RX_FIFO_11</twBEL></twPathDel><twLogDel>2.614</twLogDel><twRouteDel>2.817</twRouteDel><twTotDel>5.431</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.000">CLK_USR_BUFGP</twDestClk><twPctLog>48.1</twPctLog><twPctRoute>51.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.390</twSlack><twSrc BELType="RAM">uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType="FF">uut_rx/DATA_RX_FIFO_21</twDest><twTotPathDel>5.209</twTotPathDel><twClkSkew dest = "1.337" src = "1.703">0.366</twClkSkew><twDelConst>6.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="20"><twSrc BELType='RAM'>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType='FF'>uut_rx/DATA_RX_FIFO_21</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X0Y7.CLKARDCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_USR_BUFGP</twSrcClk><twPathDel><twSite>RAMB36_X0Y7.DOADOU10</twSite><twDelType>Trcko_DO</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twComp><twBEL>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X2Y66.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.595</twDelInfo><twComp>uut_rx/dout&lt;21&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X2Y66.CLK</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.434</twDelInfo><twComp>uut_rx/DATA_RX_FIFO&lt;21&gt;</twComp><twBEL>uut_rx/DATA_RX_FIFO_21</twBEL></twPathDel><twLogDel>2.614</twLogDel><twRouteDel>2.595</twRouteDel><twTotDel>5.209</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.000">CLK_USR_BUFGP</twDestClk><twPctLog>50.2</twPctLog><twPctRoute>49.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt><twConstPath twDataPathType = "twDataPathMaxDelay" constType="period"><twSlack>0.405</twSlack><twSrc BELType="RAM">uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType="FF">uut_rx/DATA_RX_FIFO_49</twDest><twTotPathDel>5.187</twTotPathDel><twClkSkew dest = "1.330" src = "1.703">0.373</twClkSkew><twDelConst>6.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="19"><twSrc BELType='RAM'>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twSrc><twDest BELType='FF'>uut_rx/DATA_RX_FIFO_49</twDest><twLogLvls>0</twLogLvls><twSrcSite>RAMB36_X0Y7.CLKARDCLKU</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">CLK_USR_BUFGP</twSrcClk><twPathDel><twSite>RAMB36_X0Y7.DOBDOU8</twSite><twDelType>Trcko_DO</twDelType><twDelInfo twEdge="twRising">2.180</twDelInfo><twComp>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twComp><twBEL>uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X2Y61.D1</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.573</twDelInfo><twComp>uut_rx/dout&lt;49&gt;</twComp></twPathDel><twPathDel><twSite>OLOGIC_X2Y61.CLK</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.434</twDelInfo><twComp>uut_rx/DATA_RX_FIFO&lt;49&gt;</twComp><twBEL>uut_rx/DATA_RX_FIFO_49</twBEL></twPathDel><twLogDel>2.614</twLogDel><twRouteDel>2.573</twRouteDel><twTotDel>5.187</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="6.000">CLK_USR_BUFGP</twDestClk><twPctLog>50.4</twPctLog><twPctRoute>49.6</twPctRoute></twDetPath></twConstPath></twPathRpt></twConst><twUnmetConstCnt>0</twUnmetConstCnt><twDataSheet twNameLen="15"><twClk2SUList twDestWidth = "7"><twDest>CLK_USR</twDest><twClk2SU><twSrc>CLK_USR</twSrc><twRiseRise>5.727</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList twDestWidth = "8"><twDest>TXCLKDIV</twDest><twClk2SU><twSrc>TXCLKDIV</twSrc><twRiseRise>5.284</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum><twErrCnt>0</twErrCnt><twScore>0</twScore><twConstCov><twPathCnt>755</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>873</twConnCnt></twConstCov><twStats><twMinPer>5.727</twMinPer><twFootnote number="1" /><twMaxFreq>174.611</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Mon Aug 25 17:19:32 2008 </twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 260 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>