hdllib.ref

FPGA之间的LVDS传输

AR blk_mem_gen_generic_cstr xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_generic_cstr.vhd sub00/vhpl35 1219478035
EN blk_mem_gen_mux NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_mux.vhd sub00/vhpl10 1219478010
AR blk_mem_gen_mux xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_mux.vhd sub00/vhpl11 1219478011
PH blk_mem_gen_pkg NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_v2_6_pkg.vhd sub00/vhpl02 1219478002
AR blk_mem_gen_prim_wrapper_v5_init xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v5_init.vhd sub00/vhpl23 1219478023
AR blk_mem_gen_prim_wrapper_v2_init xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v2_init.vhd sub00/vhpl31 1219478031
EN bindec NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_bindec.vhd sub00/vhpl08 1219478008
PH blk_mem_gen_getinit_pkg NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_getinit_pkg.vhd sub00/vhpl04 1219478004
PH blk_mem_min_area_pkg NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_min_area_pkg.vhd sub00/vhpl06 1219478006
MO ramb36sdp_wrap NULL E:\ISEworks\LVDS\LVDS_4to1\tmp\_cg\_bbx\blk_mem_gen_v2_6\ramb36sdp_wrap.v vlg77/ramb36sdp__wrap.bin 1219478004
AR blk_mem_gen_prim_wrapper_v5 xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v5.vhd sub00/vhpl21 1219478021
EN blk_mem_gen_prim_wrapper_v4_init NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v4_init.vhd sub00/vhpl26 1219478026
EN blk_mem_gen_v2_6_xst NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_v2_6_xst.vhd sub00/vhpl42 1219478042
EN blk_mem_input_block NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_input_block.vhd sub00/vhpl36 1219478036
EN blk_mem_gen_prim_wrapper_s3a NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3a.vhd sub00/vhpl16 1219478016
PB blk_mem_gen_pkg blk_mem_gen_pkg E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_v2_6_pkg.vhd sub00/vhpl03 1219478003
AR blk_mem_gen_prim_wrapper_s3adsp xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3adsp.vhd sub00/vhpl13 1219478013
AR blk_mem_gen_prim_wrapper_s3a_init xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3a_init.vhd sub00/vhpl19 1219478019
AR blk_mem_gen_prim_wrapper_s3adsp_init xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3adsp_init.vhd sub00/vhpl15 1219478015
EN blk_mem_gen_prim_wrapper_s3adsp_init NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3adsp_init.vhd sub00/vhpl14 1219478014
EN blk_mem_gen_prim_wrapper_v5_init NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v5_init.vhd sub00/vhpl22 1219478022
AR blk_mem_gen_prim_wrapper_v4 xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v4.vhd sub00/vhpl25 1219478025
EN blk_mem_output_block NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_output_block.vhd sub00/vhpl38 1219478038
EN blk_mem_gen_prim_wrapper_s3a_init NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3a_init.vhd sub00/vhpl18 1219478018
AR blk_mem_gen_v2_6_xst xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_v2_6_xst.vhd sub00/vhpl43 1219478043
AR blk_mem_output_block xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_output_block.vhd sub00/vhpl39 1219478039
PB blk_mem_gen_getinit_pkg blk_mem_gen_getinit_pkg E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_getinit_pkg.vhd sub00/vhpl05 1219478005
AR blk_mem_gen_top xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_top.vhd sub00/vhpl41 1219478041
EN blk_mem_gen_prim_wrapper_s3adsp NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3adsp.vhd sub00/vhpl12 1219478012
PH blk_mem_gen_v2_6_defaults NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_v2_6_defaults.vhd sub00/vhpl01 1219478001
EN blk_mem_gen_generic_cstr NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_generic_cstr.vhd sub00/vhpl34 1219478034
PH blk_mem_gen_v2_6_xst_comp NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_v2_6_xst_comp.vhd sub00/vhpl00 1219478000
AR blk_mem_input_block xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_input_block.vhd sub00/vhpl37 1219478037
EN blk_mem_gen_top NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_top.vhd sub00/vhpl40 1219478040
AR blk_mem_gen_prim_wrapper_v4_init xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v4_init.vhd sub00/vhpl27 1219478027
EN blk_mem_gen_prim_wrapper_v2 NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v2.vhd sub00/vhpl28 1219478028
EN blk_mem_gen_prim_wrapper_v4 NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v4.vhd sub00/vhpl24 1219478024
AR blk_mem_gen_prim_wrapper_v2 xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v2.vhd sub00/vhpl29 1219478029
EN blk_mem_gen_prim_wrapper_v5 NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v5.vhd sub00/vhpl20 1219478020
EN blk_mem_gen_prim_wrapper_v2_init NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_v2_init.vhd sub00/vhpl30 1219478030
AR bindec xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_bindec.vhd sub00/vhpl09 1219478009
PB blk_mem_min_area_pkg blk_mem_min_area_pkg E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_min_area_pkg.vhd sub00/vhpl07 1219478007
EN blk_mem_gen_prim_width NULL E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_width.vhd sub00/vhpl32 1219478032
AR blk_mem_gen_prim_width xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_width.vhd sub00/vhpl33 1219478033
AR blk_mem_gen_prim_wrapper_s3a xilinx E:/ISEworks/LVDS/LVDS_4to1/tmp/_cg/_bbx/blk_mem_gen_v2_6/blk_mem_gen_prim_wrapper_s3a.vhd sub00/vhpl17 1219478017