test_tx.vhd

FPGA之间的LVDS传输

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-- Company: 
-- Engineer:
--
-- Create Date:   10:50:50 08/20/2008
-- Design Name:   
-- Module Name:   E:/ISEworks/LVDS/xapp860/test_tx.vhd
-- Project Name:  xapp860
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DDR_6TO1_16CHAN_RT_TX
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY test_tx IS
END test_tx;
 
ARCHITECTURE behavior OF test_tx IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DDR_6TO1_16CHAN_RT_TX
    PORT(
         DATA_TX_P : OUT  std_logic_vector(15 downto 0);
         DATA_TX_N : OUT  std_logic_vector(15 downto 0);
         CLOCK_TX_P : OUT  std_logic;
         CLOCK_TX_N : OUT  std_logic;
         TXCLK : IN  std_logic;
         TXCLKDIV : IN  std_logic;
         DATA_TO_OSERDES : IN  std_logic_vector(95 downto 0);
         RESET : IN  std_logic;
         TRAINING_DONE : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal TXCLK : std_logic := '0';
   signal TXCLKDIV : std_logic := '0';
   signal DATA_TO_OSERDES : std_logic_vector(95 downto 0) := (others => '0');
   signal RESET : std_logic := '1';
   signal TRAINING_DONE : std_logic := '0';

 	--Outputs
   signal DATA_TX_P : std_logic_vector(15 downto 0);
   signal DATA_TX_P2 : std_logic_vector(15 downto 0);
   signal DATA_TX_N : std_logic_vector(15 downto 0);
   signal DATA_TX_N2 : std_logic_vector(15 downto 0);
   signal CLOCK_TX_P : std_logic;
   signal CLOCK_TX_N : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DDR_6TO1_16CHAN_RT_TX PORT MAP (
          DATA_TX_P => DATA_TX_P,
          DATA_TX_N => DATA_TX_N,
          CLOCK_TX_P => CLOCK_TX_P,
          CLOCK_TX_N => CLOCK_TX_N,
          TXCLK => TXCLK,
          TXCLKDIV => TXCLKDIV,
          DATA_TO_OSERDES => DATA_TO_OSERDES,
          RESET => RESET,
          TRAINING_DONE => TRAINING_DONE
        );
 
  
  
   TXCLK_process :process
   begin
		TXCLK <= '0';
		wait for 1.5 ns;
		TXCLK <= '1';
		wait for 1.5 ns;
   end process;
	
	TXCLKDIV_process :process
   begin
		TXCLKDIV <= '0';
		wait for 4.5 ns;
		TXCLKDIV <= '1';
		wait for 4.5 ns;
   end process;
	
	
	--process(DATA_TX_P)
	--	begin
		DATA_TX_P2 <= TRANSPORT DATA_TX_P after 100 ns;
	--end process;
	DATA_TX_N2 <= DATA_TX_N after 100 ns;
   
--   CLOCK_RX_P <= CLOCK_TX_P after 100 ns;
--   CLOCK_RX_N <= CLOCK_TX_N after 100 ns;
--	DATA_RX_P <= DATA_TX_P ;
--	DATA_RX_N <= DATA_TX_N ;
--   
--   CLOCK_RX_P <= CLOCK_TX_P ;
--   CLOCK_RX_N <= CLOCK_TX_N ;
   

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 1ms.
      
		wait for 5 us;
		RESET <= '0';
           -- insert stimulus here 

      wait;
   end process;

END;