复件 ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal Sh211 : STD_LOGIC; 
  signal Sh122 : STD_LOGIC; 
  signal Sh123 : STD_LOGIC; 
  signal Sh1251 : STD_LOGIC; 
  signal Sh1241 : STD_LOGIC; 
  signal Sh1761 : STD_LOGIC; 
  signal Sh1771 : STD_LOGIC; 
  signal Sh921 : STD_LOGIC; 
  signal Sh931 : STD_LOGIC; 
  signal Sh1122 : STD_LOGIC; 
  signal Sh1131 : STD_LOGIC; 
  signal Sh114 : STD_LOGIC; 
  signal Sh115 : STD_LOGIC; 
  signal Sh83 : STD_LOGIC; 
  signal Sh82 : STD_LOGIC; 
  signal Sh1851 : STD_LOGIC; 
  signal Sh1842 : STD_LOGIC; 
  signal Sh1162 : STD_LOGIC; 
  signal Sh1171 : STD_LOGIC; 
  signal Sh801 : STD_LOGIC; 
  signal Sh811 : STD_LOGIC; 
  signal Mshreg_RESET_SM_15_4993 : STD_LOGIC; 
  signal Sh1202 : STD_LOGIC; 
  signal Sh1211 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal Sh881 : STD_LOGIC; 
  signal Sh891 : STD_LOGIC; 
  signal Sh2161 : STD_LOGIC; 
  signal Sh2171 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NLW_ISERDES_CLOCK_RX_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_INC_CAPTURE_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_BITSLIP_CAPTURE_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_DEC_CAPTURE_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_RESET_SM_15_Q15_UNCONNECTED : STD_LOGIC; 
  signal TAP_COUNTER_00_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_01_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_10_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_02_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_11_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_03_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_12_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_04_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_13_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_05_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_14_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_06_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_15_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_07_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_08_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_09_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal DATA_RX_IDLY : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal DATA_RX_IDLY_MON : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal DATA_FROM_ISERDES_MON : STD_LOGIC_VECTOR ( 95 downto 0 ); 
  signal CHAN_SEL : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_0_channel_counter_counter_value_preserver : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal INC_TO_ISERDES : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal ICE_TO_ISERDES_RT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal ICE_TO_ISERDES : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal INC_TO_ISERDES_RT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_total_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_1_channel_counter_counter_value_preserver : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal ICE_TO_MONITOR_RT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal CHAN_SEL_RT : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal INC_TO_MONITOR_RT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_counter0_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BITSLIP_TO_ISERDES : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_1_delay_counter_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_0_delay_counter_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_counter1_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RESET_SM : STD_LOGIC_VECTOR ( 15 downto 15 ); 
  signal BIT_ALIGN_MACHINE_0_RXDATA_PREV : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal DATA_TO_MACHINE : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal DATA_TO_RT : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal MONITOR_TO_RT : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_STORE_STATUS : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_SAMPLE_WINDOW : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_CVS : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_addsub0000 : STD_LOGIC_VECTOR ( 5 downto 4 ); 
  signal TAP_COUNTER_15_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_11_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_04_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_14_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_12_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_10_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_01_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal TAP_COUNTER_05_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_09_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_02_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_06_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_08_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_07_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_13_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_00_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_03_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal DATA_TO_RT_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal MONITOR_TO_RT_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal DATA_TO_MACHINE_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_1_delay_counter_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal TAP_COUNTER_11_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_04_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_15_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_counter1_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal TAP_COUNTER_14_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_counter0_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_total_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal TAP_COUNTER_12_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_05_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_06_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_07_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_10_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_01_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_02_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_13_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_08_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_00_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_03_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal TAP_COUNTER_09_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_0_delay_counter_counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  DATA_FROM_ISERDES_3_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y154"
    )
    port map (
      I => DATA_FROM_ISERDES_3_OBUF_5805,
      O => DATA_FROM_ISERDES(3)
    );
  DATA_FROM_ISERDES_4_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y156"
    )
    port map (
      I => DATA_FROM_ISERDES_4_OBUF_5806,
      O => DATA_FROM_ISERDES(4)
    );
  DATA_FROM_ISERDES_5_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y142"
    )
    port map (
      I => DATA_FROM_ISERDES_5_OBUF_5807,
      O => DATA_FROM_ISERDES(5)
    );
  DATA_FROM_ISERDES_6_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y145"
    )
    port map (
      I => DATA_FROM_ISERDES_6_OBUF_5808,
      O => DATA_FROM_ISERDES(6)
    );
  DATA_FROM_ISERDES_7_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y142"
    )
    port map (
      I => DATA_FROM_ISERDES_7_OBUF_5809,
      O => DATA_FROM_ISERDES(7)
    );
  DATA_FROM_ISERDES_8_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y143"
    )
    port map (
      I => DATA_FROM_ISERDES_8_OBUF_5810,
      O => DATA_FROM_ISERDES(8)
    );
  DATA_FROM_ISERDES_9_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y144"
    )
    port map (
      I => DATA_FROM_ISERDES_9_OBUF_5811,
      O => DATA_FROM_ISERDES(9)
    );
  DATA_FROM_ISERDES_10_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y141"
    )
    port map (
      I => DATA_FROM_ISERDES_10_OBUF_5812,
      O => DATA_FROM_ISERDES(10)
    );
  DATA_FROM_ISERDES_11_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y137"
    )
    port map (
      I => DATA_FROM_ISERDES_11_OBUF_5813,
      O => DATA_FROM_ISERDES(11)
    );
  DATA_FROM_ISERDES_18_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y133"
    )
    port map (
      I => DATA_FROM_ISERDES_18_OBUF_5836,
      O => DATA_FROM_ISERDES(18)
    );
  DATA_FROM_ISERDES_51_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y138"
    )
    port map (
      I => DATA_FROM_ISERDES_51_OBUF_5837,
      O => DATA_FROM_ISERDES(51)
    );
  DATA_FROM_ISERDES_43_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y148"
    )
    port map (
      I => DATA_FROM_ISERDES_43_OBUF_5838,
      O => DATA_FROM_ISERDES(43)
    );
  DATA_FROM_ISERDES_35_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y154"
    )
    port map (
      I => DATA_FROM_ISERDES_35_OBUF_5839,
      O => DATA_FROM_ISERDES(35)
    );
  DATA_FROM_ISERDES_27_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y125"
    )
    port map (
      I => DATA_FROM_ISERDES_27_OBUF_5840,
      O => DATA_FROM_ISERDES(27)
    );
  DATA_FROM_ISERDES_19_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y131"
    )
    port map (
      I => DATA_FROM_ISERDES_19_OBUF_5841,
      O => DATA_FROM_ISERDES(19)
    );
  DATA_FROM_ISERDES_60_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y131"
    )
    port map (
      I => DATA_FROM_ISERDES_60_OBUF_5842,
      O => DATA_FROM_ISERDES(60)
    );
  DATA_FROM_ISERDES_52_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y132"
    )
    port map (
      I => DATA_FROM_ISERDES_52_OBUF_5843,
      O => DATA_FROM_ISERDES(52)
    );
  DATA_FROM_ISERDES_44_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y147"
    )
    port map (
      I => DATA_FROM_ISERDES_44_OBUF_5844,
      O => DATA_FROM_ISERDES(44)
    );
  DATA_FROM_ISERDES_36_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y152"
    )
    port map (
      I => DATA_FROM_ISERDES_36_OBUF_5845,
      O => DATA_FROM_ISERDES(36)
    );
  DATA_FROM_ISERDES_28_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y123"
    )
    port map (
      I => DATA_FROM_ISERDES_28_OBUF_5846,
      O => DATA_FROM_ISERDES(28)
    );
  DATA_FROM_ISERDES_61_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y130"
    )
    port map (
      I => DATA_FROM_ISERDES_61_OBUF_5847,
      O => DATA_FROM_ISERDES(61)
    );
  DATA_FROM_ISERDES_53_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y139"
    )
    port map (
      I => DATA_FROM_ISERDES_53_OBUF_5848,
      O => DATA_FROM_ISERDES(53)
    );
  DATA_FROM_ISERDES_45_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y146"
    )
    port map (
      I => DATA_FROM_ISERDES_45_OBUF_5849,
      O => DATA_FROM_ISERDES(45)
    );
  DATA_FROM_ISERDES_37_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X0Y148"
    )
    port map (
      I => DATA_FROM_ISERDES_37_OBUF_5850,
      O => DATA_FROM_ISERDES(37)
    );
  DATA_FROM_ISERDES_29_OBUF : X_OBUF
    generic map(
      LOC => "IOB_X2Y123"
    )
    port map (
      I => DATA_FROM_ISERDES_29_OBUF_5851,
      O => DATA_FROM_ISERDES(29)
    );
  DATA_FROM_ISERDES_70_OBUF : X_OBUF