复件 ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal ISERDES_RX_DATA_09_D : STD_LOGIC; 
  signal IODELAY_RX_MON_00_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_00_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_01_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_01_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_10_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_10_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_02_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_02_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_11_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_11_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_03_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_03_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_12_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_12_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_04_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_04_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_13_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_13_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_05_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_05_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_14_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_14_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_06_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_06_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_15_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_15_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_07_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_07_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_08_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_08_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_09_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_09_ODATAIN : STD_LOGIC; 
  signal ISERDES_RX_MON_00_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_00_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_00_O : STD_LOGIC; 
  signal ISERDES_RX_MON_00_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_00_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_00_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_00_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_00_D : STD_LOGIC; 
  signal ISERDES_RX_MON_01_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_01_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_01_O : STD_LOGIC; 
  signal ISERDES_RX_MON_01_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_01_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_01_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_01_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_01_D : STD_LOGIC; 
  signal ISERDES_RX_MON_10_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_10_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_10_O : STD_LOGIC; 
  signal ISERDES_RX_MON_10_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_10_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_10_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_10_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_10_D : STD_LOGIC; 
  signal ISERDES_RX_MON_02_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_02_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_02_O : STD_LOGIC; 
  signal ISERDES_RX_MON_02_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_02_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_02_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_02_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_02_D : STD_LOGIC; 
  signal ISERDES_RX_MON_11_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_11_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_11_O : STD_LOGIC; 
  signal ISERDES_RX_MON_11_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_11_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_11_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_11_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_11_D : STD_LOGIC; 
  signal ISERDES_RX_MON_03_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_03_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_03_O : STD_LOGIC; 
  signal ISERDES_RX_MON_03_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_03_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_03_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_03_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_03_D : STD_LOGIC; 
  signal ISERDES_RX_MON_12_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_12_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_12_O : STD_LOGIC; 
  signal ISERDES_RX_MON_12_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_12_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_12_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_12_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_12_D : STD_LOGIC; 
  signal ISERDES_RX_MON_04_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_04_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_04_O : STD_LOGIC; 
  signal ISERDES_RX_MON_04_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_04_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_04_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_04_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_04_D : STD_LOGIC; 
  signal ISERDES_RX_MON_13_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_13_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_13_O : STD_LOGIC; 
  signal ISERDES_RX_MON_13_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_13_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_13_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_13_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_13_D : STD_LOGIC; 
  signal ISERDES_RX_MON_05_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_05_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_05_O : STD_LOGIC; 
  signal ISERDES_RX_MON_05_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_05_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_05_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_05_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_05_D : STD_LOGIC; 
  signal ISERDES_RX_MON_14_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_14_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_14_O : STD_LOGIC; 
  signal ISERDES_RX_MON_14_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_14_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_14_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_14_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_14_D : STD_LOGIC; 
  signal ISERDES_RX_MON_06_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_06_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_06_O : STD_LOGIC; 
  signal ISERDES_RX_MON_06_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_06_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_06_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_06_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_06_D : STD_LOGIC; 
  signal ISERDES_RX_MON_15_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_15_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_15_O : STD_LOGIC; 
  signal ISERDES_RX_MON_15_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_15_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_15_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_15_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_15_D : STD_LOGIC; 
  signal ISERDES_RX_MON_07_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_07_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_07_O : STD_LOGIC; 
  signal ISERDES_RX_MON_07_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_07_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_07_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_07_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_07_D : STD_LOGIC; 
  signal ISERDES_RX_MON_08_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_08_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_08_O : STD_LOGIC; 
  signal ISERDES_RX_MON_08_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_08_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_08_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_08_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_08_D : STD_LOGIC; 
  signal ISERDES_RX_MON_09_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_09_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_09_O : STD_LOGIC; 
  signal ISERDES_RX_MON_09_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_09_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_09_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_09_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_09_D : STD_LOGIC; 
  signal IODELAY_RX_DATA_00_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_00_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_01_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_01_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_10_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_10_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_02_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_02_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_11_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_11_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_03_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_03_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_12_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_12_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_04_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_04_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_13_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_13_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_05_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_05_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_14_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_14_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_06_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_06_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_15_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_15_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_07_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_07_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_08_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_08_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_09_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_09_ODATAIN : STD_LOGIC; 
  signal ISERDES_CLOCK_RX_ODATAIN : STD_LOGIC; 
  signal Mmux_DATA_TO_MACHINE_mux0001_6_f7_1518 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f7_1517 : STD_LOGIC; 
  signal Mmux_DATA_TO_MACHINE_mux0001_8_1516 : STD_LOGIC; 
  signal Mmux_DATA_TO_MACHINE_mux0001_71_1515 : STD_LOGIC; 
  signal CHAN_SEL_3_8_1514 : STD_LOGIC; 
  signal CHAN_SEL_3_71_1513 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f72 : STD_LOGIC; 
  signal CHAN_SEL_3_82_1625 : STD_LOGIC; 
  signal CHAN_SEL_3_75_1624 : STD_LOGIC; 
  signal Sh58 : STD_LOGIC; 
  signal Sh59 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f73 : STD_LOGIC; 
  signal CHAN_SEL_3_83_1775 : STD_LOGIC; 
  signal CHAN_SEL_3_77_1774 : STD_LOGIC; 
  signal CHAN_SEL_3_73_1780 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f71 : STD_LOGIC; 
  signal CHAN_SEL_3_81_1777 : STD_LOGIC; 
  signal Sh154 : STD_LOGIC; 
  signal Sh155 : STD_LOGIC; 
  signal Sh151 : STD_LOGIC; 
  signal Sh150 : STD_LOGIC; 
  signal Mshreg_INC_CAPTURE_2_1921 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f74 : STD_LOGIC; 
  signal CHAN_SEL_3_84_2005 : STD_LOGIC; 
  signal CHAN_SEL_3_79_2004 : STD_LOGIC; 
  signal Sh55 : STD_LOGIC; 
  signal Sh54 : STD_LOGIC; 
  signal Sh531 : STD_LOGIC; 
  signal Sh521 : STD_LOGIC; 
  signal Sh1441 : STD_LOGIC; 
  signal Sh1451 : STD_LOGIC; 
  signal Sh63 : STD_LOGIC; 
  signal Sh62 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd1_In : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In21661_2481 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In2166 : STD_LOGIC; 
  signal Sh1481 : STD_LOGIC; 
  signal Sh1491 : STD_LOGIC; 
  signal Sh1521 : STD_LOGIC; 
  signal Sh1531 : STD_LOGIC; 
  signal Sh561 : STD_LOGIC; 
  signal Sh571 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd2_In : STD_LOGIC; 
  signal Sh161 : STD_LOGIC; 
  signal Sh171 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd3_In_2984 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_DATA_ALIGNED_RTx : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd2_In : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd1_In : STD_LOGIC; 
  signal Sh2121 : STD_LOGIC; 
  signal Sh2131 : STD_LOGIC; 
  signal Sh95 : STD_LOGIC; 
  signal Sh94 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd3_In_3147 : STD_LOGIC; 
  signal N95 : STD_LOGIC; 
  signal N96 : STD_LOGIC; 
  signal Sh251 : STD_LOGIC; 
  signal Sh241 : STD_LOGIC; 
  signal Sh26 : STD_LOGIC; 
  signal Sh27 : STD_LOGIC; 
  signal Sh30 : STD_LOGIC; 
  signal Sh31 : STD_LOGIC; 
  signal Mshreg_BITSLIP_CAPTURE_2_3301 : STD_LOGIC; 
  signal Sh51 : STD_LOGIC; 
  signal Sh50 : STD_LOGIC; 
  signal Sh146 : STD_LOGIC; 
  signal Sh147 : STD_LOGIC; 
  signal Mshreg_DEC_CAPTURE_2_3389 : STD_LOGIC; 
  signal Sh291 : STD_LOGIC; 
  signal Sh281 : STD_LOGIC; 
  signal Sh19 : STD_LOGIC; 
  signal Sh18 : STD_LOGIC; 
  signal Sh201 : STD_LOGIC; 
  signal Sh2111_3455 : STD_LOGIC; 
  signal Sh222 : STD_LOGIC; 
  signal Sh223 : STD_LOGIC; 
  signal Sh219 : STD_LOGIC; 
  signal Sh218 : STD_LOGIC; 
  signal Sh127 : STD_LOGIC; 
  signal Sh126 : STD_LOGIC; 
  signal Sh191_3519 : STD_LOGIC; 
  signal Sh190 : STD_LOGIC; 
  signal Sh23 : STD_LOGIC; 
  signal Sh22 : STD_LOGIC; 
  signal Sh481 : STD_LOGIC; 
  signal Sh491 : STD_LOGIC; 
  signal Sh851 : STD_LOGIC; 
  signal Sh841 : STD_LOGIC; 
  signal Sh601 : STD_LOGIC; 
  signal Sh611 : STD_LOGIC; 
  signal Sh1561 : STD_LOGIC; 
  signal Sh1571 : STD_LOGIC; 
  signal Sh91 : STD_LOGIC; 
  signal Sh90 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In : STD_LOGIC; 
  signal Sh1802 : STD_LOGIC; 
  signal Sh1811 : STD_LOGIC; 
  signal N88 : STD_LOGIC; 
  signal N87 : STD_LOGIC; 
  signal N75 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_DATA_ALIGNEDx : STD_LOGIC; 
  signal Sh2081 : STD_LOGIC; 
  signal Sh2091 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd1_In_3965 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In : STD_LOGIC; 
  signal Sh1881 : STD_LOGIC; 
  signal Sh1891 : STD_LOGIC; 
  signal Sh182 : STD_LOGIC; 
  signal Sh183 : STD_LOGIC; 
  signal Sh118 : STD_LOGIC; 
  signal Sh119 : STD_LOGIC; 
  signal Sh86 : STD_LOGIC; 
  signal Sh87 : STD_LOGIC; 
  signal Sh2201 : STD_LOGIC; 
  signal Sh2211 : STD_LOGIC; 
  signal Sh158 : STD_LOGIC; 
  signal Sh159 : STD_LOGIC; 
  signal Sh214 : STD_LOGIC; 
  signal Sh215 : STD_LOGIC; 
  signal Sh186 : STD_LOGIC; 
  signal Sh187 : STD_LOGIC; 
  signal Sh178 : STD_LOGIC; 
  signal Sh179 : STD_LOGIC; 
  signal Sh210 : STD_LOGIC;