复件 ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal RESOURCE_SHARING_CONTROL_1_UD_DELAY : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_UD_DELAY : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N22 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal INC_DATABUS : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd1_6466 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal DEC_CAPTURE_0_Q : STD_LOGIC; 
  signal DEC_CAPTURE_2_Q : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_COUNT1 : STD_LOGIC; 
  signal N02 : STD_LOGIC; 
  signal CHAN_SEL_3_64_6514 : STD_LOGIC; 
  signal Mmux_MONITOR_TO_RT_mux0001_71_6515 : STD_LOGIC; 
  signal BITSLIP_CAPTURE_0_Q : STD_LOGIC; 
  signal BITSLIP_CAPTURE_2_Q : STD_LOGIC; 
  signal CHAN_SEL_RT_3_61_6524 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_62_6525 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_71_6526 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_63_6527 : STD_LOGIC; 
  signal N80 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_72_6533 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_64_6534 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_65_6535 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_73_6536 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_74_6538 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_75_6539 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_77_6541 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_76_6542 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_79_6544 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_78_6545 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_711_6547 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_710_6548 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N20 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_lt0001 : STD_LOGIC; 
  signal N84 : STD_LOGIC; 
  signal N85 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N12 : STD_LOGIC; 
  signal N62 : STD_LOGIC; 
  signal N611 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_eq0000 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In82_6559 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In57_6560 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In38_6561 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_611_6562 : STD_LOGIC; 
  signal Mmux_DATA_TO_RT_mux0001_71_6563 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_621_6564 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_631_6565 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_721_6566 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_641_6567 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_731_6568 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_741_6570 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_751_6571 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_771_6573 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_761_6574 : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd10 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_STORE_DATA_PREV : STD_LOGIC; 
  signal CHAN_SEL_RT_3_791_6583 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_781_6584 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_STATUS : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In267_6595 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In_bdd4 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In148_6598 : STD_LOGIC; 
  signal N52 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd3_In_6601 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_gt0001 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In103_6606 : STD_LOGIC; 
  signal N44 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal INC_CAPTURE_3_Q : STD_LOGIC; 
  signal Mmux_DATA_TO_RT_mux0001_6_6611 : STD_LOGIC; 
  signal Mmux_DATA_TO_RT_mux0001_7_6612 : STD_LOGIC; 
  signal Mmux_DATA_TO_MACHINE_mux0001_6_6614 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_machine_counter_N23 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_machine_counter_N21 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In2193_6618 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In2350_6619 : STD_LOGIC; 
  signal START_ALIGN : STD_LOGIC; 
  signal Mmux_MONITOR_TO_RT_mux0001_6_6625 : STD_LOGIC; 
  signal Mmux_MONITOR_TO_RT_mux0001_7_6626 : STD_LOGIC; 
  signal BITSLIP_PULSE_6628 : STD_LOGIC; 
  signal N72 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_lt00021_6631 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_lt00022_6636 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In2330_6639 : STD_LOGIC; 
  signal START_ALIGN_RT : STD_LOGIC; 
  signal CHAN_SEL_RT_3_6_6641 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_7_6642 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal BITSLIP_CAPTURE_3_Q : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd1_1_6648 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd1_In_bdd5 : STD_LOGIC; 
  signal N42 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In95_6651 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N35 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In31_6653 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd18 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_STORE : STD_LOGIC; 
  signal N93 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_16 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_17 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_1_6663 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd3_1_6664 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd1_In : STD_LOGIC; 
  signal DEC_CAPTURE_3_Q : STD_LOGIC; 
  signal N64 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal N59 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N16 : STD_LOGIC; 
  signal CHAN_SEL_3_61_6671 : STD_LOGIC; 
  signal CHAN_SEL_3_62_6672 : STD_LOGIC; 
  signal CHAN_SEL_3_63_6673 : STD_LOGIC; 
  signal CHAN_SEL_3_6_6674 : STD_LOGIC; 
  signal Mmux_DATA_TO_RT_mux0001_8_6675 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_8_6676 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_811_6677 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_821_6678 : STD_LOGIC; 
  signal Mmux_MONITOR_TO_RT_mux0001_8_6679 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_85_6680 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_831_6681 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_841_6682 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_83_6683 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_84_6684 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_81_6685 : STD_LOGIC; 
  signal CHAN_SEL_RT_3_82_6686 : STD_LOGIC; 
  signal CHAN_SEL_3_72_6687 : STD_LOGIC; 
  signal CHAN_SEL_3_74_6688 : STD_LOGIC; 
  signal CHAN_SEL_3_76_6690 : STD_LOGIC; 
  signal CHAN_SEL_3_78_6691 : STD_LOGIC; 
  signal N92 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In1241_6693 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In2260_6694 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In233_6695 : STD_LOGIC; 
  signal N47 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In279_6698 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_ne0000126_6701 : STD_LOGIC; 
  signal Mmux_DATA_TO_MACHINE_mux0001_7_6702 : STD_LOGIC; 
  signal CHAN_SEL_3_7_6703 : STD_LOGIC; 
  signal DATA_ALIGNED_RT : STD_LOGIC; 
  signal N82 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In109_6712 : STD_LOGIC; 
  signal N74 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In37_6714 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In38_6716 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal N66 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In148_6721 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_18 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_19 : STD_LOGIC; 
  signal DATA_RX_N_0_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_1_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_2_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_3_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_4_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_5_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_6_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_7_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_0_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_8_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_1_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_9_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_2_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_3_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_4_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_5_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_6_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_7_INBUF_DS : STD_LOGIC; 
  signal CLK200_INBUF_B : STD_LOGIC; 
  signal DATA_RX_N_10_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_11_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_12_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_13_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_14_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_15_INBUF_DS : STD_LOGIC; 
  signal RESET_INBUF_B : STD_LOGIC; 
  signal DATA_RX_P_10_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_11_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_12_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_13_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_14_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_15_INBUF_DS : STD_LOGIC; 
  signal INC_PAD_INBUF_B : STD_LOGIC; 
  signal RT_MANUAL_DISABLE_INBUF_B : STD_LOGIC; 
  signal BITSLIP_PAD_INBUF_B : STD_LOGIC; 
  signal DATA_RX_P_8_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_9_INBUF_DS : STD_LOGIC; 
  signal CLOCK_RX_P_INBUF_DS : STD_LOGIC; 
  signal IDELAYCTRL_RESET_INBUF_B : STD_LOGIC; 
  signal DEC_PAD_INBUF_B : STD_LOGIC; 
  signal IDLY_RESET_INBUF_B : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_CLK_INT : STD_LOGIC;