复件 ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.37
--  \   \         Application: netgen
--  /   /         Filename: DDR_6TO1_16CHAN_RT_RX_timesim.vhd
-- /___/   /\     Timestamp: Wed Aug 20 08:44:17 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 1 -pcf DDR_6TO1_16CHAN_RT_RX.pcf -rpw 100 -tpw 0 -ar Structure -tm DDR_6TO1_16CHAN_RT_RX -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim DDR_6TO1_16CHAN_RT_RX.ncd DDR_6TO1_16CHAN_RT_RX_timesim.vhd 
-- Device	: 5vsx50tff1136-1 (PRODUCTION 1.61 2008-05-28)
-- Input file	: DDR_6TO1_16CHAN_RT_RX.ncd
-- Output file	: E:\ISEworks\LVDS\xapp860\netgen\par\DDR_6TO1_16CHAN_RT_RX_timesim.vhd
-- # of Entities	: 1
-- Design Name	: DDR_6TO1_16CHAN_RT_RX
-- Xilinx	: K:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity DDR_6TO1_16CHAN_RT_RX is
  port (
    RXCLKDIV : out STD_LOGIC; 
    RESET : in STD_LOGIC := 'X'; 
    RT_MANUAL_DISABLE : in STD_LOGIC := 'X'; 
    IDLY_RESET : in STD_LOGIC := 'X'; 
    DEC_PAD : in STD_LOGIC := 'X'; 
    CLOCK_RX_N : in STD_LOGIC := 'X'; 
    CLOCK_RX_P : in STD_LOGIC := 'X'; 
    IDELAY_READY : out STD_LOGIC; 
    CLK200 : in STD_LOGIC := 'X'; 
    BITSLIP_PAD : in STD_LOGIC := 'X'; 
    RXCLK : out STD_LOGIC; 
    IDELAYCTRL_RESET : in STD_LOGIC := 'X'; 
    INC_PAD : in STD_LOGIC := 'X'; 
    TRAINING_DONE : out STD_LOGIC; 
    TAP_00 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_01 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_02 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_03 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_04 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_05 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_10 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_06 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_11 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_07 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_12 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_08 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_13 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_09 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_14 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_15 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_CLK : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    DATA_FROM_ISERDES : out STD_LOGIC_VECTOR ( 95 downto 0 ); 
    DATA_RX_N : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    DATA_RX_P : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end DDR_6TO1_16CHAN_RT_RX;

architecture Structure of DDR_6TO1_16CHAN_RT_RX is
  signal DATA_FROM_ISERDES_3_OBUF_5805 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_4_OBUF_5806 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_5_OBUF_5807 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_6_OBUF_5808 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_7_OBUF_5809 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_8_OBUF_5810 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_9_OBUF_5811 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_10_OBUF_5812 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_11_OBUF_5813 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_20_OBUF_5814 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_12_OBUF_5815 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_21_OBUF_5816 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_13_OBUF_5817 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_30_OBUF_5818 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_22_OBUF_5819 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_14_OBUF_5820 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_31_OBUF_5821 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_23_OBUF_5822 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_15_OBUF_5823 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_40_OBUF_5824 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_32_OBUF_5825 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_24_OBUF_5826 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_16_OBUF_5827 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_41_OBUF_5828 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_33_OBUF_5829 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_25_OBUF_5830 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_17_OBUF_5831 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_50_OBUF_5832 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_42_OBUF_5833 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_34_OBUF_5834 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_26_OBUF_5835 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_18_OBUF_5836 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_51_OBUF_5837 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_43_OBUF_5838 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_35_OBUF_5839 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_27_OBUF_5840 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_19_OBUF_5841 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_60_OBUF_5842 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_52_OBUF_5843 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_44_OBUF_5844 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_36_OBUF_5845 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_28_OBUF_5846 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_61_OBUF_5847 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_53_OBUF_5848 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_45_OBUF_5849 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_37_OBUF_5850 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_29_OBUF_5851 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_70_OBUF_5852 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_62_OBUF_5853 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_54_OBUF_5854 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_46_OBUF_5855 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_38_OBUF_5856 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_71_OBUF_5857 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_63_OBUF_5858 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_55_OBUF_5859 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_47_OBUF_5860 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_39_OBUF_5861 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_80_OBUF_5862 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_72_OBUF_5863 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_64_OBUF_5864 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_56_OBUF_5865 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_48_OBUF_5866 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_81_OBUF_5867 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_73_OBUF_5868 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_65_OBUF_5869 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_57_OBUF_5870 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_49_OBUF_5871 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_90_OBUF_5872 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_82_OBUF_5873 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_74_OBUF_5874 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_66_OBUF_5875 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_58_OBUF_5876 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_91_OBUF_5877 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_83_OBUF_5878 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_75_OBUF_5879 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_67_OBUF_5880 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_59_OBUF_5881 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_92_OBUF_5882 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_84_OBUF_5883 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_76_OBUF_5884 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_68_OBUF_5885 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_93_OBUF_5886 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_85_OBUF_5887 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_77_OBUF_5888 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_69_OBUF_5889 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_94_OBUF_5890 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_86_OBUF_5891 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_78_OBUF_5892 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_95_OBUF_5893 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_87_OBUF_5894 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_79_OBUF_5895 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_88_OBUF_5896 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_89_OBUF_5897 : STD_LOGIC; 
  signal TRAINING_DONE_OBUF_5995 : STD_LOGIC; 
  signal RESET_IBUF_6014 : STD_LOGIC; 
  signal RXCLKDIV_OBUF_6018 : STD_LOGIC; 
  signal IDELAY_READY_OBUF_6067 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_0_OBUF_6071 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_1_OBUF_6072 : STD_LOGIC; 
  signal DATA_FROM_ISERDES_2_OBUF_6073 : STD_LOGIC; 
  signal BITSLIP_00 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal RXCLK_TEMP : STD_LOGIC; 
  signal BITSLIP_01 : STD_LOGIC; 
  signal BITSLIP_10 : STD_LOGIC; 
  signal BITSLIP_02 : STD_LOGIC; 
  signal BITSLIP_11 : STD_LOGIC; 
  signal BITSLIP_03 : STD_LOGIC; 
  signal BITSLIP_12 : STD_LOGIC; 
  signal BITSLIP_04 : STD_LOGIC; 
  signal BITSLIP_13 : STD_LOGIC; 
  signal BITSLIP_05 : STD_LOGIC; 
  signal BITSLIP_14 : STD_LOGIC; 
  signal BITSLIP_06 : STD_LOGIC; 
  signal BITSLIP_15 : STD_LOGIC; 
  signal BITSLIP_07 : STD_LOGIC; 
  signal BITSLIP_08 : STD_LOGIC; 
  signal BITSLIP_09 : STD_LOGIC; 
  signal CLK200_BUFGP : STD_LOGIC; 
  signal RX_MON_CE_00 : STD_LOGIC; 
  signal RX_DATA_RESET : STD_LOGIC; 
  signal RX_MON_INC_00 : STD_LOGIC; 
  signal RX_MON_CE_01 : STD_LOGIC; 
  signal RX_MON_INC_01 : STD_LOGIC; 
  signal RX_MON_CE_10 : STD_LOGIC; 
  signal RX_MON_INC_10 : STD_LOGIC; 
  signal RX_MON_CE_02 : STD_LOGIC; 
  signal RX_MON_INC_02 : STD_LOGIC; 
  signal RX_MON_CE_11 : STD_LOGIC; 
  signal RX_MON_INC_11 : STD_LOGIC; 
  signal RX_MON_CE_03 : STD_LOGIC; 
  signal RX_MON_INC_03 : STD_LOGIC; 
  signal RX_MON_CE_12 : STD_LOGIC; 
  signal RX_MON_INC_12 : STD_LOGIC; 
  signal RX_MON_CE_04 : STD_LOGIC; 
  signal RX_MON_INC_04 : STD_LOGIC; 
  signal RX_MON_CE_13 : STD_LOGIC; 
  signal RX_MON_INC_13 : STD_LOGIC; 
  signal RX_MON_CE_05 : STD_LOGIC; 
  signal RX_MON_INC_05 : STD_LOGIC; 
  signal RX_MON_CE_14 : STD_LOGIC; 
  signal RX_MON_INC_14 : STD_LOGIC; 
  signal RX_MON_CE_06 : STD_LOGIC; 
  signal RX_MON_INC_06 : STD_LOGIC; 
  signal RX_MON_CE_15 : STD_LOGIC; 
  signal RX_MON_INC_15 : STD_LOGIC; 
  signal RX_MON_CE_07 : STD_LOGIC; 
  signal RX_MON_INC_07 : STD_LOGIC; 
  signal RX_MON_CE_08 : STD_LOGIC; 
  signal RX_MON_INC_08 : STD_LOGIC; 
  signal RX_MON_CE_09 : STD_LOGIC; 
  signal RX_MON_INC_09 : STD_LOGIC; 
  signal CLOCK_RX_ISERDES_OUT : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_1 : STD_LOGIC; 
  signal RX_DATA_CE_00 : STD_LOGIC; 
  signal RX_DATA_INC_00 : STD_LOGIC; 
  signal RX_DATA_CE_01 : STD_LOGIC; 
  signal RX_DATA_INC_01 : STD_LOGIC; 
  signal RX_DATA_CE_10 : STD_LOGIC; 
  signal RX_DATA_INC_10 : STD_LOGIC; 
  signal RX_DATA_CE_02 : STD_LOGIC; 
  signal RX_DATA_INC_02 : STD_LOGIC; 
  signal RX_DATA_CE_11 : STD_LOGIC; 
  signal RX_DATA_INC_11 : STD_LOGIC; 
  signal RX_DATA_CE_03 : STD_LOGIC; 
  signal RX_DATA_INC_03 : STD_LOGIC; 
  signal RX_DATA_CE_12 : STD_LOGIC; 
  signal RX_DATA_INC_12 : STD_LOGIC; 
  signal RX_DATA_CE_04 : STD_LOGIC; 
  signal RX_DATA_INC_04 : STD_LOGIC; 
  signal RX_DATA_CE_13 : STD_LOGIC; 
  signal RX_DATA_INC_13 : STD_LOGIC; 
  signal RX_DATA_CE_05 : STD_LOGIC; 
  signal RX_DATA_INC_05 : STD_LOGIC; 
  signal RX_DATA_CE_14 : STD_LOGIC; 
  signal RX_DATA_INC_14 : STD_LOGIC; 
  signal RX_DATA_CE_06 : STD_LOGIC; 
  signal RX_DATA_INC_06 : STD_LOGIC; 
  signal RX_DATA_CE_15 : STD_LOGIC; 
  signal RX_DATA_INC_15 : STD_LOGIC; 
  signal RX_DATA_CE_07 : STD_LOGIC; 
  signal RX_DATA_INC_07 : STD_LOGIC; 
  signal RX_DATA_CE_08 : STD_LOGIC; 
  signal RX_DATA_INC_08 : STD_LOGIC; 
  signal RX_DATA_CE_09 : STD_LOGIC; 
  signal RX_DATA_INC_09 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f7_0_6291 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_COUNT : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_UD : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_RESET : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_cmp_lt0000 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd3_6304 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd1_6305 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd2_6306 : STD_LOGIC; 
  signal DATA_ALIGNED : STD_LOGIC; 
  signal CHAN_SEL_3_6_f71_0 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f72_0 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f73_0 : STD_LOGIC; 
  signal CHAN_SEL_3_6_f74_0 : STD_LOGIC; 
  signal Mmux_DATA_TO_MACHINE_mux0001_6_f7_0 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_6313 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd6 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd1_6315 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_6316 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_6317 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_6318 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd23 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_cmp_lt0000 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd2_6321 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd1_6322 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd3_6323 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_6326 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd3_6327 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In260_6328 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_ne0000 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In144_6330 : STD_LOGIC; 
  signal N75_0 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In211_6332 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_6333 : STD_LOGIC; 
  signal INC_FROM_MACHINE : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_COUNT_CHAN : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal INC_PULSE_6352 : STD_LOGIC; 
  signal DEC_PULSE_6353 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_6366 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_COUNT_SAMPLE : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal ICE_FROM_MACHINE : STD_LOGIC; 
  signal INC_CAPTURE_0_Q : STD_LOGIC; 
  signal INC_CAPTURE_2_Q : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_COUNT_CHAN : STD_LOGIC; 
  signal ICE_MONITOR : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal ICE_DATABUS : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd2 : STD_LOGIC; 
  signal INC_MONITOR : STD_LOGIC; 
  signal BITSLIP_FROM_MACHINE : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_COUNT0 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N41 : STD_LOGIC; 
  signal N61 : STD_LOGIC;