lvds_bist_top_timesim.vhd

FPGA之间的LVDS传输

      ADR5 => VCC,
      ADR4 => count,
      O => NlwRenamedSig_OI_counter_value(0)
    );
  NlwBlock_channel_counter_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_channel_counter_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity count_to_128 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    ud : in STD_LOGIC := 'X'; 
    count : in STD_LOGIC := 'X'; 
    counter_value : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end count_to_128;

architecture Structure of count_to_128 is
  signal N21 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwRenamedSig_OI_counter_value : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  counter_value(6) <= NlwRenamedSig_OI_counter_value(6);
  counter_value(5) <= NlwRenamedSig_OI_counter_value(5);
  counter_value(4) <= NlwRenamedSig_OI_counter_value(4);
  counter_value(3) <= NlwRenamedSig_OI_counter_value(3);
  counter_value(2) <= NlwRenamedSig_OI_counter_value(2);
  counter_value(1) <= NlwRenamedSig_OI_counter_value(1);
  counter_value(0) <= NlwRenamedSig_OI_counter_value(0);
  Maddsub_counter_value_int_addsub0000_cy_4_121 : X_LUT6
    generic map(
      LOC => "SLICE_X88Y83",
      INIT => X"CCCC000000000000"
    )
    port map (
      ADR0 => VCC,
      ADR3 => VCC,
      ADR2 => VCC,
      ADR5 => NlwRenamedSig_OI_counter_value(1),
      ADR4 => NlwRenamedSig_OI_counter_value(0),
      ADR1 => NlwRenamedSig_OI_counter_value(2),
      O => N23
    );
  counter_value_int_mux0001_3_11 : X_LUT6
    generic map(
      LOC => "SLICE_X88Y83",
      INIT => X"FFFFFFFFFFFFCCCC"
    )
    port map (
      ADR0 => VCC,
      ADR3 => VCC,
      ADR2 => VCC,
      ADR4 => NlwRenamedSig_OI_counter_value(0),
      ADR5 => NlwRenamedSig_OI_counter_value(1),
      ADR1 => NlwRenamedSig_OI_counter_value(2),
      O => N21
    );
  counter_value_int_2 : X_FF
    generic map(
      LOC => "SLICE_X88Y84",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(4),
      O => NlwRenamedSig_OI_counter_value(2),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_4_1 : X_LUT6
    generic map(
      LOC => "SLICE_X88Y84",
      INIT => X"7E817E81F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => NlwRenamedSig_OI_counter_value(0),
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(2),
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR5 => ud,
      O => counter_value_int_mux0001(4)
    );
  counter_value_int_1 : X_FF
    generic map(
      LOC => "SLICE_X88Y84",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(5),
      O => NlwRenamedSig_OI_counter_value(1),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_5_1 : X_LUT6
    generic map(
      LOC => "SLICE_X88Y84",
      INIT => X"5AA55AA5F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => VCC,
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(1),
      ADR0 => NlwRenamedSig_OI_counter_value(0),
      ADR5 => ud,
      O => counter_value_int_mux0001(5)
    );
  counter_value_int_0 : X_FF
    generic map(
      LOC => "SLICE_X88Y84",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(6),
      O => NlwRenamedSig_OI_counter_value(0),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_6_1 : X_LUT6
    generic map(
      LOC => "SLICE_X88Y84",
      INIT => X"00FFFF0000FF0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR4 => ud,
      ADR5 => ud,
      O => counter_value_int_mux0001(6)
    );
  counter_value_int_6 : X_FF
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(0),
      O => NlwRenamedSig_OI_counter_value(6),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_0_1 : X_LUT6
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => X"7E817E81F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => NlwRenamedSig_OI_counter_value(5),
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(6),
      ADR0 => Maddsub_counter_value_int_addsub0000_cy(4),
      ADR5 => ud,
      O => counter_value_int_mux0001(0)
    );
  counter_value_int_3 : X_FF
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(3),
      O => NlwRenamedSig_OI_counter_value(3),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_3_2 : X_LUT6
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => X"7FFE8001CCCC0000"
    )
    port map (
      ADR2 => NlwRenamedSig_OI_counter_value(0),
      ADR1 => ud,
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR4 => NlwRenamedSig_OI_counter_value(3),
      ADR3 => NlwRenamedSig_OI_counter_value(2),
      ADR5 => ud,
      O => counter_value_int_mux0001(3)
    );
  counter_value_int_5 : X_FF
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(1),
      O => NlwRenamedSig_OI_counter_value(5),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_1_1 : X_LUT6
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => X"5AA55AA5F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => VCC,
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(5),
      ADR0 => Maddsub_counter_value_int_addsub0000_cy(4),
      ADR5 => ud,
      O => counter_value_int_mux0001(1)
    );
  Maddsub_counter_value_int_addsub0000_cy_4_11 : X_LUT6
    generic map(
      LOC => "SLICE_X89Y83",
      INIT => X"CE0A0A0ACE080A08"
    )
    port map (
      ADR0 => ud,
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      ADR2 => ud,
      ADR5 => N21,
      ADR3 => NlwRenamedSig_OI_counter_value(4),
      ADR4 => N23,
      O => Maddsub_counter_value_int_addsub0000_cy(4)
    );
  counter_value_int_mux0001_2_Q : X_MUX2
    generic map(
      LOC => "SLICE_X89Y84"
    )
    port map (
      IA => N22,
      IB => N31,
      O => counter_value_int_mux0001(2),
      SEL => ud
    );
  counter_value_int_mux0001_2_F : X_LUT6
    generic map(
      LOC => "SLICE_X89Y84",
      INIT => X"AAAA0000AAA90000"
    )
    port map (
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR4 => ud,
      ADR0 => NlwRenamedSig_OI_counter_value(4),
      ADR5 => NlwRenamedSig_OI_counter_value(1),
      ADR1 => NlwRenamedSig_OI_counter_value(2),
      ADR2 => NlwRenamedSig_OI_counter_value(3),
      O => N22
    );
  counter_value_int_4 : X_FF
    generic map(
      LOC => "SLICE_X89Y84",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(2),
      O => NlwRenamedSig_OI_counter_value(4),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_2_G : X_LUT6
    generic map(
      LOC => "SLICE_X89Y84",
      INIT => X"6AAAAAAAAAAAAAAA"
    )
    port map (
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      ADR4 => ud,
      ADR2 => NlwRenamedSig_OI_counter_value(0),
      ADR0 => NlwRenamedSig_OI_counter_value(4),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      ADR3 => NlwRenamedSig_OI_counter_value(1),
      O => N31
    );
  NlwBlock_delay_counter_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_delay_counter_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity RESOURCE_SHARING_CONTROL is
  port (
    CLK : in STD_LOGIC := 'X'; 
    RST : in STD_LOGIC := 'X'; 
    REPEAT_PROC : in STD_LOGIC := 'X'; 
    DATA_ALIGNED : in STD_LOGIC := 'X'; 
    START_ALIGN : out STD_LOGIC; 
    ALL_CHANNELS_ALIGNED : out STD_LOGIC; 
    CHAN_SEL : out STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end RESOURCE_SHARING_CONTROL;

architecture Structure of RESOURCE_SHARING_CONTROL is
  component count_to_128
    port (
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      ud : in STD_LOGIC := 'X'; 
      count : in STD_LOGIC := 'X'; 
      counter_value : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
    );
  end component;
  component count_to_16x
    port (
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      count : in STD_LOGIC := 'X'; 
      counter_value : out STD_LOGIC_VECTOR ( 4 downto 0 ) 
    );
  end component;
  signal UD_DELAY : STD_LOGIC; 
  signal COUNT_CHAN : STD_LOGIC; 
  signal CS_FSM_FFd3_3791 : STD_LOGIC; 
  signal CS_FSM_FFd1_3792 : STD_LOGIC; 
  signal CS_FSM_FFd2_3793 : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal CS_cmp_lt0000 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal CS_FSM_FFd1_In : STD_LOGIC; 
  signal CS_FSM_FFd2_In : STD_LOGIC; 
  signal CS_FSM_FFd3_In_3746 : STD_LOGIC; 
  signal NLW_delay_counter_counter_value_2_UNCONNECTED : STD_LOGIC; 
  signal NLW_delay_counter_counter_value_1_UNCONNECTED : STD_LOGIC; 
  signal NLW_delay_counter_counter_value_0_UNCONNECTED : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwRenamedSig_OI_CHAN_SEL : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal COUNT_VALUE : STD_LOGIC_VECTOR ( 6 downto 3 ); 
begin
  CHAN_SEL(4) <= NlwRenamedSig_OI_CHAN_SEL(4);
  CHAN_SEL(3) <= NlwRenamedSig_OI_CHAN_SEL(3);
  CHAN_SEL(2) <= NlwRenamedSig_OI_CHAN_SEL(2);
  CHAN_SEL(1) <= NlwRenamedSig_OI_CHAN_SEL(1);
  CHAN_SEL(0) <= NlwRenamedSig_OI_CHAN_SEL(0);
  delay_counter : count_to_128
    port map (
      clk => CLK,
      rst => RST,
      ud => UD_DELAY,
      count => UD_DELAY,
      counter_value(6) => COUNT_VALUE(6),
      counter_value(5) => COUNT_VALUE(5),
      counter_value(4) => COUNT_VALUE(4),
      counter_value(3) => COUNT_VALUE(3),
      counter_value(2) => NLW_delay_counter_counter_value_2_UNCONNECTED,
      counter_value(1) => NLW_delay_counter_counter_value_1_UNCONNECTED,
      counter_value(0) => NLW_delay_counter_counter_value_0_UNCONNECTED
    );
  channel_counter : count_to_16x
    port map (
      clk => CLK,
      rst => RST,
      count => COUNT_CHAN,
      counter_value(4) => NlwRenamedSig_OI_CHAN_SEL(4),
      counter_value(3) => NlwRenamedSig_OI_CHAN_SEL(3),
      counter_value(2) => NlwRenamedSig_OI_CHAN_SEL(2),
      counter_value(1) => NlwRenamedSig_OI_CHAN_SEL(1),
      counter_value(0) => NlwRenamedSig_OI_CHAN_SEL(0)
    );
  ALL_CHANNELS_ALIGNED1 : X_LUT6
    generic map(
      LOC => "SLICE_X89Y72",
      INIT => X"000000000000CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR3 => VCC,
      ADR2 => VCC,
      ADR5 => CS_FSM_FFd3_3791,
      ADR1 => CS_FSM_FFd1_3792,
      ADR4 => CS_FSM_FFd2_3793,
      O => ALL_CHANNELS_ALIGNED
    );
  CS_FSM_Out71 : X_LUT6
    generic map(
      LOC => "SLICE_X89Y81",
      INIT => X"03C303C303C303C3"
    )
    port map (
      ADR0 => VCC,
      ADR5 => VCC,
      ADR4 => VCC,
      ADR1 => CS_FSM_FFd1_3792,
      ADR2 => CS_FSM_FFd3_3791,
      ADR3 => CS_FSM_FFd2_3793,
      O => UD_DELAY
    );
  CS_cmp_lt00001 : X_LUT6
    generic map(
      LOC => "SLICE_X93Y81",
      INIT => X"0000000000000055"
    )
    port map (
      ADR2 => VCC,
      ADR1 => VCC,
      ADR5 => COUNT_VALUE(6),
      ADR4 => COUNT_VALUE(5),
      ADR0 => COUNT_VALUE(4),
      ADR3 => COUNT_VALUE(3),
      O => CS_cmp_lt0000
    );
  CS_FSM_FFd3_In_SW0 : X_LUT6
    generic map(
      LOC => "SLICE_X93Y81",
      INIT => X"CFCCCCCC3333F0F3"
    )
    port map (
      ADR0 => VCC,
      ADR2 => CS_cmp_lt0000,
      ADR5 => CS_FSM_FFd3_3791,
      ADR1 => CS_FSM_FFd2_3793,
      ADR4 => CS_FSM_FFd1_3792,
      ADR3 => DATA_ALIGNED,
      O => N0
    );
  CS_FSM_FFd2 : X_SFF
    generic map(
      LOC => "SLICE_X94Y81",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => CLK,
      I => CS_FSM_FFd2_In,
      O => CS_FSM_FFd2_3793,
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  CS_FSM_FFd2_In1 : X_LUT6
    generic map(
      LOC => "SLICE_X94Y81",
      INIT => X"00000000FFFFFF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => CS_FSM_FFd2_3793,
      ADR5 => CS_FSM_FFd1_3792,
      ADR4 => CS_FSM_FFd3_3791,
      O => CS_FSM_FFd2_In
    );
  CS_FSM_FFd1 : X_SFF
    gene