lvds_bist_top_timesim.vhd

FPGA之间的LVDS传输

      LOC => "SLICE_X107Y69",
      INIT => X"FFFAFFFAFFFAFFFA"
    )
    port map (
      ADR4 => VCC,
      ADR1 => VCC,
      ADR5 => VCC,
      ADR0 => COUNT_VALUE_SAMPLE(6),
      ADR3 => COUNT_VALUE_SAMPLE(4),
      ADR2 => COUNT_VALUE_SAMPLE(5),
      O => N20
    );
  CURRENT_STATE_FSM_FFd4_In143 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y69",
      INIT => X"5555555455555544"
    )
    port map (
      ADR3 => COUNT_VALUE_SAMPLE(2),
      ADR0 => CURRENT_STATE_FSM_FFd3_4405,
      ADR1 => COUNT_VALUE_SAMPLE(3),
      ADR2 => COUNT_VALUE_SAMPLE(0),
      ADR5 => COUNT_VALUE_SAMPLE(1),
      ADR4 => N20,
      O => CURRENT_STATE_FSM_FFd4_In143_4416
    );
  CURRENT_STATE_cmp_lt000111 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y70",
      INIT => X"00000000005F00FF"
    )
    port map (
      ADR1 => VCC,
      ADR5 => COUNT_VALUE_SAMPLE(3),
      ADR3 => N20,
      ADR2 => COUNT_VALUE_SAMPLE(0),
      ADR0 => COUNT_VALUE_SAMPLE(1),
      ADR4 => COUNT_VALUE_SAMPLE(2),
      O => CURRENT_STATE_cmp_lt0001
    );
  CURRENT_STATE_FSM_FFd4_In128 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y70",
      INIT => X"5050505050500000"
    )
    port map (
      ADR3 => VCC,
      ADR1 => VCC,
      ADR5 => CURRENT_STATE_cmp_ne0000_4402,
      ADR2 => CURRENT_STATE_FSM_FFd4_4393,
      ADR0 => CURRENT_STATE_FSM_FFd5_4395,
      ADR4 => CURRENT_STATE_cmp_lt0001,
      O => CURRENT_STATE_FSM_FFd4_In128_4401
    );
  CURRENT_STATE_FSM_FFd3_In_SW3 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y72",
      INIT => X"F0F0FFDFB0B0FFDF"
    )
    port map (
      ADR2 => CURRENT_STATE_FSM_FFd5_4395,
      ADR4 => CURRENT_STATE_FSM_FFd4_4393,
      ADR5 => CURRENT_STATE_cmp_ne0000_4402,
      ADR1 => N20,
      ADR0 => CURRENT_STATE_FSM_FFd3_4405,
      ADR3 => N36,
      O => N14
    );
  CURRENT_STATE_FSM_FFd4_In21 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y73",
      INIT => X"F8D8D8D888888888"
    )
    port map (
      ADR0 => CURRENT_STATE_FSM_FFd5_4395,
      ADR5 => CURRENT_STATE_FSM_FFd3_4405,
      ADR2 => CURRENT_STATE_FSM_FFd4_4393,
      ADR3 => CURRENT_STATE_FSM_FFd2_4408,
      ADR4 => N26,
      ADR1 => CURRENT_STATE_FSM_FFd1_4409,
      O => N13
    );
  CURRENT_STATE_FSM_FFd5_In8 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y73",
      INIT => X"0000010300000303"
    )
    port map (
      ADR2 => COUNT_VALUE(6),
      ADR4 => COUNT_VALUE(5),
      ADR1 => COUNT_VALUE(4),
      ADR5 => COUNT_VALUE(3),
      ADR3 => COUNT_VALUE(2),
      ADR0 => N01,
      O => N26
    );
  CURRENT_STATE_FSM_Out191 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y74",
      INIT => X"C040C040C040C040"
    )
    port map (
      ADR4 => VCC,
      ADR5 => VCC,
      ADR2 => CURRENT_STATE_FSM_FFd2_4408,
      ADR1 => CURRENT_STATE_FSM_FFd5_4395,
      ADR0 => CURRENT_STATE_FSM_FFd3_4405,
      ADR3 => CURRENT_STATE_FSM_FFd4_4393,
      O => COUNT
    );
  CURRENT_STATE_FSM_FFd1_In37_SW0 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y74",
      INIT => X"FFFFFFFFFFFFF0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR3 => VCC,
      ADR4 => COUNT_VALUE(6),
      ADR2 => COUNT_VALUE(5),
      ADR5 => COUNT_VALUE(4),
      O => N12
    );
  CURRENT_STATE_FSM_Out201 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y76",
      INIT => X"CCFF33CCFFCC33CC"
    )
    port map (
      ADR0 => VCC,
      ADR2 => VCC,
      ADR1 => CURRENT_STATE_FSM_FFd4_4393,
      ADR3 => CURRENT_STATE_FSM_FFd2_4408,
      ADR5 => CURRENT_STATE_FSM_FFd3_4405,
      ADR4 => CURRENT_STATE_FSM_FFd5_4395,
      O => UD
    );
  CURRENT_STATE_cmp_ne0000 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y79",
      INIT => X"FF3FFFCFFFF3FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR5 => RXDATA(2),
      ADR2 => RXDATA_PREV(2),
      ADR4 => RXDATA(3),
      ADR1 => RXDATA_PREV(3),
      ADR3 => N8,
      O => CURRENT_STATE_cmp_ne0000_4402
    );
  CURRENT_STATE_FSM_FFd4_In92 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y79",
      INIT => X"7777333377773337"
    )
    port map (
      ADR5 => COUNT_VALUE_SAMPLE(6),
      ADR2 => COUNT_VALUE_SAMPLE(5),
      ADR3 => COUNT_VALUE_SAMPLE(4),
      ADR0 => CURRENT_STATE_FSM_FFd2_4408,
      ADR1 => CURRENT_STATE_FSM_FFd4_4393,
      ADR4 => CURRENT_STATE_cmp_ne0000_4402,
      O => CURRENT_STATE_FSM_FFd4_In92_4413
    );
  CURRENT_STATE_FSM_FFd4_In10 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y80",
      INIT => X"000000F000000000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR4 => RXDATA(2),
      ADR5 => RXDATA(0),
      ADR3 => RXDATA(1),
      ADR2 => RXDATA(3),
      O => CURRENT_STATE_FSM_FFd4_In10_4394
    );
  CURRENT_STATE_FSM_Out211 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y84",
      INIT => X"0AA0005A0AA0005A"
    )
    port map (
      ADR5 => VCC,
      ADR1 => VCC,
      ADR4 => CURRENT_STATE_FSM_FFd2_4408,
      ADR2 => CURRENT_STATE_FSM_FFd3_4405,
      ADR0 => CURRENT_STATE_FSM_FFd4_4393,
      ADR3 => CURRENT_STATE_FSM_FFd5_4395,
      O => ICE
    );
  CURRENT_STATE_FSM_Out181 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y84",
      INIT => X"0A00005A0A00005A"
    )
    port map (
      ADR5 => VCC,
      ADR1 => VCC,
      ADR4 => CURRENT_STATE_FSM_FFd2_4408,
      ADR2 => CURRENT_STATE_FSM_FFd3_4405,
      ADR0 => CURRENT_STATE_FSM_FFd4_4393,
      ADR3 => CURRENT_STATE_FSM_FFd5_4395,
      O => INC
    );
  CURRENT_STATE_cmp_ne0000_SW0 : X_LUT6
    generic map(
      LOC => "SLICE_X108Y79",
      INIT => X"6666FFFFFFFF6666"
    )
    port map (
      ADR2 => VCC,
      ADR3 => VCC,
      ADR1 => RXDATA_PREV(1),
      ADR5 => RXDATA_PREV(0),
      ADR0 => RXDATA(1),
      ADR4 => RXDATA(0),
      O => N8
    );
  CURRENT_STATE_FSM_FFd2_In95 : X_LUT6
    generic map(
      LOC => "SLICE_X109Y70",
      INIT => X"0000011115550111"
    )
    port map (
      ADR4 => CURRENT_STATE_FSM_FFd4_4393,
      ADR5 => CURRENT_STATE_FSM_FFd3_4405,
      ADR3 => COUNT_VALUE_SAMPLE(1),
      ADR0 => COUNT_VALUE_SAMPLE(3),
      ADR1 => COUNT_VALUE_SAMPLE(2),
      ADR2 => COUNT_VALUE_SAMPLE(0),
      O => CURRENT_STATE_FSM_FFd2_In95_4407
    );
  CURRENT_STATE_FSM_FFd3_In_SW4 : X_LUT6
    generic map(
      LOC => "SLICE_X109Y73",
      INIT => X"FF00FF030FFF0CFF"
    )
    port map (
      ADR0 => VCC,
      ADR5 => CURRENT_STATE_FSM_FFd3_4405,
      ADR3 => CURRENT_STATE_FSM_FFd4_4393,
      ADR4 => CURRENT_STATE_cmp_ne0000_4402,
      ADR2 => CURRENT_STATE_FSM_FFd5_4395,
      ADR1 => CURRENT_STATE_cmp_lt0001,
      O => N15
    );
  CURRENT_STATE_FSM_Out231 : X_LUT6
    generic map(
      LOC => "SLICE_X109Y78",
      INIT => X"FFFDFDFFFFFDFDFF"
    )
    port map (
      ADR5 => VCC,
      ADR0 => CURRENT_STATE_FSM_FFd2_4408,
      ADR4 => CURRENT_STATE_FSM_FFd4_4393,
      ADR3 => CURRENT_STATE_FSM_FFd3_4405,
      ADR1 => CURRENT_STATE_FSM_FFd5_4395,
      ADR2 => CURRENT_STATE_FSM_FFd1_4409,
      O => STORE_DATA_PREV
    );
  bit3 : X_SFF
    generic map(
      LOC => "SLICE_X109Y79",
      INIT => '0'
    )
    port map (
      CE => STORE_DATA_PREV,
      CLK => RXCLKDIV,
      I => RXDATA(3),
      O => RXDATA_PREV(3),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit2 : X_SFF
    generic map(
      LOC => "SLICE_X109Y79",
      INIT => '0'
    )
    port map (
      CE => STORE_DATA_PREV,
      CLK => RXCLKDIV,
      I => RXDATA(2),
      O => RXDATA_PREV(2),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit1 : X_SFF
    generic map(
      LOC => "SLICE_X109Y79",
      INIT => '0'
    )
    port map (
      CE => STORE_DATA_PREV,
      CLK => RXCLKDIV,
      I => RXDATA(1),
      O => RXDATA_PREV(1),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit0 : X_SFF
    generic map(
      LOC => "SLICE_X109Y79",
      INIT => '0'
    )
    port map (
      CE => STORE_DATA_PREV,
      CLK => RXCLKDIV,
      I => RXDATA(0),
      O => RXDATA_PREV(0),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  NlwBlock_BIT_ALIGN_MACHINE_0_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_BIT_ALIGN_MACHINE_0_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity count_to_16x is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    count : in STD_LOGIC := 'X'; 
    counter_value : out STD_LOGIC_VECTOR ( 4 downto 0 ) 
  );
end count_to_16x;

architecture Structure of count_to_16x is
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwRenamedSig_OI_counter_value : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal counter_value_preserver : STD_LOGIC_VECTOR ( 4 downto 0 ); 
begin
  counter_value(4) <= NlwRenamedSig_OI_counter_value(4);
  counter_value(3) <= NlwRenamedSig_OI_counter_value(3);
  counter_value(2) <= NlwRenamedSig_OI_counter_value(2);
  counter_value(1) <= NlwRenamedSig_OI_counter_value(1);
  counter_value(0) <= NlwRenamedSig_OI_counter_value(0);
  counter_value_preserver_4 : X_FF
    generic map(
      LOC => "SLICE_X106Y87",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => NlwRenamedSig_OI_counter_value(4),
      O => counter_value_preserver(4),
      SET => GND,
      RST => rst
    );
  temp_4_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y87",
      INIT => X"7F80FF00FF00FF00"
    )
    port map (
      ADR1 => counter_value_preserver(3),
      ADR2 => counter_value_preserver(2),
      ADR5 => counter_value_preserver(1),
      ADR3 => counter_value_preserver(4),
      ADR0 => counter_value_preserver(0),
      ADR4 => count,
      O => NlwRenamedSig_OI_counter_value(4)
    );
  counter_value_preserver_3 : X_FF
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => NlwRenamedSig_OI_counter_value(3),
      O => counter_value_preserver(3),
      SET => GND,
      RST => rst
    );
  temp_3_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => X"3FC0FF00FF00FF00"
    )
    port map (
      ADR0 => VCC,
      ADR4 => counter_value_preserver(2),
      ADR1 => counter_value_preserver(1),
      ADR3 => counter_value_preserver(3),
      ADR5 => counter_value_preserver(0),
      ADR2 => count,
      O => NlwRenamedSig_OI_counter_value(3)
    );
  counter_value_preserver_2 : X_FF
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => NlwRenamedSig_OI_counter_value(2),
      O => counter_value_preserver(2),
      SET => GND,
      RST => rst
    );
  temp_2_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => X"3FC03FC0FF00FF00"
    )
    port map (
      ADR0 => VCC,
      ADR4 => VCC,
      ADR5 => counter_value_preserver(1),
      ADR3 => counter_value_preserver(2),
      ADR1 => counter_value_preserver(0),
      ADR2 => count,
      O => NlwRenamedSig_OI_counter_value(2)
    );
  counter_value_preserver_1 : X_FF
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => NlwRenamedSig_OI_counter_value(1),
      O => counter_value_preserver(1),
      SET => GND,
      RST => rst
    );
  temp_1_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => X"55AAFF0055AAFF00"
    )
    port map (
      ADR5 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => counter_value_preserver(1),
      ADR0 => counter_value_preserver(0),
      ADR4 => count,
      O => NlwRenamedSig_OI_counter_value(1)
    );
  counter_value_preserver_0 : X_FF
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => NlwRenamedSig_OI_counter_value(0),
      O => counter_value_preserver(0),
      SET => GND,
      RST => rst
    );
  temp_0_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y87",
      INIT => X"00FFFF0000FFFF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => counter_value_preserver(0),