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📄 lvds_bist_top_timesim.vhd

📁 FPGA之间的LVDS传输
💻 VHD
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    generic map(      LOC => "SLICE_X103Y68",      INIT => X"0040004000400040"    )    port map (      ADR4 => VCC,      ADR5 => VCC,      ADR3 => CURRENT_STATE_FSM_FFd5_4395,      ADR1 => CURRENT_STATE_FSM_FFd2_4408,      ADR0 => CURRENT_STATE_FSM_FFd4_4393,      ADR2 => CURRENT_STATE_FSM_FFd3_4405,      O => STORE    );  count_reg : X_SFF    generic map(      LOC => "SLICE_X103Y80",      INIT => '0'    )    port map (      CE => VCC,      CLK => RXCLKDIV,      I => DATA_ALIGNEDx,      O => DATA_ALIGNED,      SSET => GND,      SRST => RST,      SET => GND,      RST => GND    );  DATA_ALIGNEDx1 : X_LUT6    generic map(      LOC => "SLICE_X103Y80",      INIT => X"C333000000030000"    )    port map (      ADR0 => VCC,      ADR4 => CURRENT_STATE_FSM_FFd1_4409,      ADR5 => CURRENT_STATE_FSM_FFd2_4408,      ADR3 => CURRENT_STATE_FSM_FFd4_4393,      ADR1 => CURRENT_STATE_FSM_FFd5_4395,      ADR2 => CURRENT_STATE_FSM_FFd3_4405,      O => DATA_ALIGNEDx    );  CURRENT_STATE_FSM_FFd5_In44 : X_LUT6    generic map(      LOC => "SLICE_X104Y69",      INIT => X"C000000000000000"    )    port map (      ADR0 => VCC,      ADR4 => N36,      ADR5 => COUNT_VALUE_SAMPLE(4),      ADR3 => COUNT_VALUE_SAMPLE(5),      ADR2 => COUNT_VALUE_SAMPLE(6),      ADR1 => CURRENT_STATE_FSM_FFd2_4408,      O => CURRENT_STATE_FSM_FFd5_In44_4425    );  CURRENT_STATE_FSM_FFd5_In127 : X_LUT6    generic map(      LOC => "SLICE_X104Y69",      INIT => X"08FF08FF080F080A"    )    port map (      ADR3 => CURRENT_STATE_cmp_ne0000_4402,      ADR5 => CURRENT_STATE_FSM_FFd5_In82_4423,      ADR0 => CURRENT_STATE_FSM_FFd5_4395,      ADR2 => CURRENT_STATE_FSM_FFd4_4393,      ADR1 => CURRENT_STATE_FSM_FFd2_4408,      ADR4 => CURRENT_STATE_FSM_FFd5_In44_4425,      O => CURRENT_STATE_FSM_FFd5_In127_4421    );  CURRENT_STATE_FSM_FFd5 : X_FF    generic map(      LOC => "SLICE_X104Y70",      INIT => '0'    )    port map (      CE => VCC,      CLK => RXCLKDIV,      I => CURRENT_STATE_FSM_FFd5_In,      O => CURRENT_STATE_FSM_FFd5_4395,      SET => GND,      RST => RST    );  CURRENT_STATE_FSM_FFd5_In324 : X_LUT6    generic map(      LOC => "SLICE_X104Y70",      INIT => X"FFFFFFF0FFCCFFCC"    )    port map (      ADR0 => VCC,      ADR5 => CURRENT_STATE_FSM_FFd3_4405,      ADR3 => CURRENT_STATE_FSM_FFd5_In36_4420,      ADR2 => CURRENT_STATE_FSM_FFd5_In250_4417,      ADR1 => CURRENT_STATE_FSM_FFd5_In127_4421,      ADR4 => CURRENT_STATE_FSM_FFd5_In289_4427,      O => CURRENT_STATE_FSM_FFd5_In    );  CURRENT_STATE_FSM_FFd5_In289 : X_LUT6    generic map(      LOC => "SLICE_X104Y70",      INIT => X"08000A0808000A08"    )    port map (      ADR5 => VCC,      ADR3 => COUNT_VALUE_SAMPLE(6),      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR0 => CURRENT_STATE_FSM_FFd4_4393,      ADR1 => N17,      ADR4 => CURRENT_STATE_cmp_lt00022_4398,      O => CURRENT_STATE_FSM_FFd5_In289_4427    );  CURRENT_STATE_FSM_FFd4 : X_FF    generic map(      LOC => "SLICE_X104Y70",      INIT => '0'    )    port map (      CE => VCC,      CLK => RXCLKDIV,      I => CURRENT_STATE_FSM_FFd4_In,      O => CURRENT_STATE_FSM_FFd4_4393,      SET => GND,      RST => RST    );  CURRENT_STATE_FSM_FFd4_In229 : X_LUT6    generic map(      LOC => "SLICE_X104Y70",      INIT => X"FFFFFFFFFF00CC00"    )    port map (      ADR0 => VCC,      ADR2 => VCC,      ADR4 => CURRENT_STATE_FSM_FFd4_In128_4401,      ADR3 => CURRENT_STATE_FSM_FFd2_4408,      ADR1 => CURRENT_STATE_FSM_FFd4_In188_4415,      ADR5 => CURRENT_STATE_FSM_FFd4_In107_4426,      O => CURRENT_STATE_FSM_FFd4_In    );  CURRENT_STATE_FSM_FFd4_In107 : X_LUT6    generic map(      LOC => "SLICE_X104Y70",      INIT => X"FFFFFFFFFFFF4040"    )    port map (      ADR3 => VCC,      ADR0 => CURRENT_STATE_FSM_FFd3_4405,      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR4 => N13,      ADR5 => CURRENT_STATE_FSM_FFd4_In55_4391,      ADR1 => CURRENT_STATE_FSM_FFd4_In92_4413,      O => CURRENT_STATE_FSM_FFd4_In107_4426    );  CURRENT_STATE_FSM_FFd3 : X_FF    generic map(      LOC => "SLICE_X104Y73",      INIT => '0'    )    port map (      CE => VCC,      CLK => RXCLKDIV,      I => CURRENT_STATE_FSM_FFd3_In_4111,      O => CURRENT_STATE_FSM_FFd3_4405,      SET => GND,      RST => RST    );  CURRENT_STATE_FSM_FFd3_In : X_LUT6    generic map(      LOC => "SLICE_X104Y73",      INIT => X"FFFF5353FFFF5353"    )    port map (      ADR5 => VCC,      ADR3 => VCC,      ADR2 => CURRENT_STATE_FSM_FFd2_4408,      ADR1 => N14,      ADR0 => N15,      ADR4 => N13,      O => CURRENT_STATE_FSM_FFd3_In_4111    );  CURRENT_STATE_FSM_FFd1_In37_SW1 : X_LUT6    generic map(      LOC => "SLICE_X104Y73",      INIT => X"EA00AA00AA00AA00"    )    port map (      ADR3 => CURRENT_STATE_FSM_FFd4_4393,      ADR2 => COUNT_VALUE(3),      ADR1 => COUNT_VALUE(2),      ADR5 => COUNT_VALUE(1),      ADR4 => COUNT_VALUE(0),      ADR0 => N12,      O => N171    );  CURRENT_STATE_FSM_FFd1 : X_FF    generic map(      LOC => "SLICE_X104Y73",      INIT => '0'    )    port map (      CE => VCC,      CLK => RXCLKDIV,      I => CURRENT_STATE_FSM_FFd1_In,      O => CURRENT_STATE_FSM_FFd1_4409,      SET => GND,      RST => RST    );  CURRENT_STATE_FSM_FFd1_In37 : X_LUT6    generic map(      LOC => "SLICE_X104Y73",      INIT => X"808000008F800F00"    )    port map (      ADR5 => SAP,      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR0 => CURRENT_STATE_FSM_FFd2_4408,      ADR3 => CURRENT_STATE_FSM_FFd1_4409,      ADR1 => CURRENT_STATE_FSM_FFd3_4405,      ADR4 => N171,      O => CURRENT_STATE_FSM_FFd1_In    );  CURRENT_STATE_cmp_lt00021 : X_LUT6    generic map(      LOC => "SLICE_X105Y65",      INIT => X"FF555F055F055500"    )    port map (      ADR1 => VCC,      ADR0 => COUNT_VALUE_SAMPLE(5),      ADR2 => COUNT_VALUE_SAMPLE(4),      ADR5 => CURRENT_STATE_addsub0000(4),      ADR3 => CURRENT_STATE_addsub0000(5),      ADR4 => N10,      O => CURRENT_STATE_cmp_lt00022_4398    );  CURRENT_STATE_cmp_lt00021_SW0 : X_LUT6    generic map(      LOC => "SLICE_X105Y65",      INIT => X"AAA8FFFE0002AAAB"    )    port map (      ADR4 => COUNT_VALUE_SAMPLE(3),      ADR1 => CVS(1),      ADR5 => CVS(4),      ADR2 => CVS(2),      ADR3 => CVS(3),      ADR0 => CURRENT_STATE_cmp_lt00021_4397,      O => N10    );  CURRENT_STATE_FSM_FFd5_In82 : X_LUT6    generic map(      LOC => "SLICE_X105Y69",      INIT => X"0000000000000030"    )    port map (      ADR0 => VCC,      ADR1 => CURRENT_STATE_FSM_FFd2_4408,      ADR5 => COUNT_VALUE_SAMPLE(6),      ADR3 => COUNT_VALUE_SAMPLE(5),      ADR2 => CURRENT_STATE_FSM_FFd4_4393,      ADR4 => COUNT_VALUE_SAMPLE(4),      O => CURRENT_STATE_FSM_FFd5_In82_4423    );  CURRENT_STATE_FSM_FFd4_In188 : X_LUT6    generic map(      LOC => "SLICE_X105Y70",      INIT => X"5550551155505500"    )    port map (      ADR4 => CURRENT_STATE_cmp_ne0000_4402,      ADR2 => CURRENT_STATE_FSM_FFd4_In143_4416,      ADR0 => CURRENT_STATE_FSM_FFd4_4393,      ADR5 => CURRENT_STATE_FSM_FFd3_4405,      ADR1 => CURRENT_STATE_cmp_lt0001,      ADR3 => CURRENT_STATE_FSM_FFd5_4395,      O => CURRENT_STATE_FSM_FFd4_In188_4415    );  CURRENT_STATE_FSM_FFd5_In36 : X_LUT6    generic map(      LOC => "SLICE_X105Y72",      INIT => X"F3F00300F3F00301"    )    port map (      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR3 => CURRENT_STATE_FSM_FFd4_4393,      ADR1 => CURRENT_STATE_FSM_FFd2_4408,      ADR4 => CURRENT_STATE_FSM_FFd1_4409,      ADR0 => SAP,      ADR5 => CURRENT_STATE_FSM_FFd3_4405,      O => CURRENT_STATE_FSM_FFd5_In36_4420    );  CURRENT_STATE_FSM_Out221 : X_LUT6    generic map(      LOC => "SLICE_X105Y83",      INIT => X"CCCC000CCCCC0000"    )    port map (      ADR0 => VCC,      ADR1 => CURRENT_STATE_FSM_FFd5_4395,      ADR2 => CURRENT_STATE_FSM_FFd2_4408,      ADR5 => CURRENT_STATE_FSM_FFd3_4405,      ADR3 => CURRENT_STATE_FSM_FFd4_4393,      ADR4 => CURRENT_STATE_FSM_FFd1_4409,      O => BITSLIP    );  CURRENT_STATE_FSM_Out171 : X_LUT6    generic map(      LOC => "SLICE_X106Y68",      INIT => X"0055FF0000AAFF00"    )    port map (      ADR2 => VCC,      ADR1 => VCC,      ADR3 => CURRENT_STATE_FSM_FFd2_4408,      ADR4 => CURRENT_STATE_FSM_FFd5_4395,      ADR5 => CURRENT_STATE_FSM_FFd3_4405,      ADR0 => CURRENT_STATE_FSM_FFd4_4393,      O => COUNT_SAMPLE    );  CURRENT_STATE_FSM_FFd4_In48 : X_LUT6    generic map(      LOC => "SLICE_X106Y70",      INIT => X"3333333300000000"    )    port map (      ADR0 => VCC,      ADR4 => VCC,      ADR2 => VCC,      ADR3 => VCC,      ADR5 => CURRENT_STATE_FSM_FFd3_4405,      ADR1 => CURRENT_STATE_FSM_FFd2_4408,      O => CURRENT_STATE_FSM_FFd4_In48_4430    );  CURRENT_STATE_FSM_FFd5_In9111 : X_LUT6    generic map(      LOC => "SLICE_X106Y70",      INIT => X"A0A0000000000000"    )    port map (      ADR3 => VCC,      ADR1 => VCC,      ADR4 => COUNT_VALUE_SAMPLE(2),      ADR5 => COUNT_VALUE_SAMPLE(3),      ADR2 => COUNT_VALUE_SAMPLE(0),      ADR0 => COUNT_VALUE_SAMPLE(1),      O => N36    );  CURRENT_STATE_FSM_FFd4_In55 : X_LUT6    generic map(      LOC => "SLICE_X106Y70",      INIT => X"5F5F5F5D00000000"    )    port map (      ADR3 => N20,      ADR2 => CURRENT_STATE_FSM_FFd4_4393,      ADR5 => CURRENT_STATE_FSM_FFd4_In48_4430,      ADR1 => CURRENT_STATE_FSM_FFd4_In10_4394,      ADR0 => CURRENT_STATE_FSM_FFd5_4395,      ADR4 => N36,      O => CURRENT_STATE_FSM_FFd4_In55_4391    );  CURRENT_STATE_FSM_FFd5_In244 : X_LUT6    generic map(      LOC => "SLICE_X106Y72",      INIT => X"8080000080800040"    )    port map (      ADR0 => CURRENT_STATE_FSM_FFd2_4408,      ADR4 => CURRENT_STATE_FSM_FFd4_4393,      ADR5 => N36,      ADR3 => N20,      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR1 => CURRENT_STATE_FSM_FFd5_In228_4418,      O => CURRENT_STATE_FSM_FFd5_In244_4431    );  CURRENT_STATE_FSM_FFd5_In250 : X_LUT6    generic map(      LOC => "SLICE_X106Y72",      INIT => X"FFFF8082FFFF0002"    )    port map (      ADR0 => CURRENT_STATE_FSM_FFd2_4408,      ADR1 => CURRENT_STATE_FSM_FFd4_4393,      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR5 => N26,      ADR4 => CURRENT_STATE_FSM_FFd5_In244_4431,      ADR3 => CURRENT_STATE_cmp_lt0001,      O => CURRENT_STATE_FSM_FFd5_In250_4417    );  CURRENT_STATE_FSM_FFd2_In197 : X_MUX2    generic map(      LOC => "SLICE_X106Y73"    )    port map (      IA => N19,      IB => N201,      O => CURRENT_STATE_FSM_FFd2_In,      SEL => CURRENT_STATE_FSM_FFd3_4405    );  CURRENT_STATE_FSM_FFd2_In197_F : X_LUT6    generic map(      LOC => "SLICE_X106Y73",      INIT => X"FFCCFF00CDCC0500"    )    port map (      ADR3 => CURRENT_STATE_FSM_FFd2_4408,      ADR2 => CURRENT_STATE_cmp_ne0000_4402,      ADR0 => CURRENT_STATE_FSM_FFd4_4393,      ADR4 => CURRENT_STATE_FSM_FFd5_4395,      ADR1 => CURRENT_STATE_FSM_FFd1_4409,      ADR5 => CURRENT_STATE_FSM_FFd2_In116_4432,      O => N19    );  CURRENT_STATE_FSM_FFd2 : X_FF    generic map(      LOC => "SLICE_X106Y73",      INIT => '0'    )    port map (      CE => VCC,      CLK => RXCLKDIV,      I => CURRENT_STATE_FSM_FFd2_In,      O => CURRENT_STATE_FSM_FFd2_4408,      SET => GND,      RST => RST    );  CURRENT_STATE_FSM_FFd2_In197_G : X_LUT6    generic map(      LOC => "SLICE_X106Y73",      INIT => X"FFEEFDEEFF55FF55"    )    port map (      ADR0 => CURRENT_STATE_FSM_FFd4_4393,      ADR5 => CURRENT_STATE_FSM_FFd5_4395,      ADR2 => CURRENT_STATE_FSM_FFd2_In116_4432,      ADR3 => CURRENT_STATE_FSM_FFd2_4408,      ADR1 => CURRENT_STATE_FSM_FFd1_4409,      ADR4 => N26,      O => N201    );  CURRENT_STATE_FSM_FFd2_In116 : X_LUT6    generic map(      LOC => "SLICE_X106Y73",      INIT => X"5050507350505050"    )    port map (      ADR5 => CURRENT_STATE_FSM_FFd2_In95_4407,      ADR4 => COUNT_VALUE_SAMPLE(5),      ADR1 => COUNT_VALUE_SAMPLE(6),      ADR3 => COUNT_VALUE_SAMPLE(4),      ADR2 => CURRENT_STATE_FSM_FFd5_4395,      ADR0 => CURRENT_STATE_FSM_FFd3_4405,      O => CURRENT_STATE_FSM_FFd2_In116_4432    );  CURRENT_STATE_FSM_FFd5_In8_SW0 : X_LUT6    generic map(      LOC => "SLICE_X106Y73",      INIT => X"F000F000F000F000"    )    port map (      ADR0 => VCC,      ADR1 => VCC,      ADR5 => VCC,      ADR4 => VCC,      ADR3 => COUNT_VALUE(1),      ADR2 => COUNT_VALUE(0),      O => N01    );  CURRENT_STATE_FSM_FFd5_In228 : X_LUT6    generic map(      LOC => "SLICE_X106Y79",      INIT => X"FFFFFFFFFF33FFFF"    )    port map (      ADR0 => VCC,      ADR2 => VCC,      ADR3 => RXDATA(1),      ADR1 => RXDATA(3),      ADR4 => RXDATA(0),      ADR5 => RXDATA(2),      O => CURRENT_STATE_FSM_FFd5_In228_4418    );  CURRENT_STATE_cmp_lt00022 : X_LUT6    generic map(      LOC => "SLICE_X107Y65",      INIT => X"22212227B227B2B7"    )    port map (      ADR3 => CVS(1),      ADR2 => CVS(2),      ADR0 => CVS(3),      ADR1 => COUNT_VALUE_SAMPLE(2),      ADR5 => COUNT_VALUE_SAMPLE(1),      ADR4 => COUNT_VALUE_SAMPLE(0),      O => CURRENT_STATE_cmp_lt00021_4397    );  CURRENT_STATE_FSM_FFd5_In51 : X_LUT6    generic map(

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