lvds_bist_top_timesim.vhd

FPGA之间的LVDS传输

  signal GND : STD_LOGIC; 
  signal NlwRenamedSig_OI_counter_value : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  counter_value(6) <= NlwRenamedSig_OI_counter_value(6);
  counter_value(5) <= NlwRenamedSig_OI_counter_value(5);
  counter_value(4) <= NlwRenamedSig_OI_counter_value(4);
  counter_value(3) <= NlwRenamedSig_OI_counter_value(3);
  counter_value(2) <= NlwRenamedSig_OI_counter_value(2);
  counter_value(1) <= NlwRenamedSig_OI_counter_value(1);
  counter_value(0) <= NlwRenamedSig_OI_counter_value(0);
  counter_value_int_3 : X_FF
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(3),
      O => NlwRenamedSig_OI_counter_value(3),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_3_2 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => X"7A80FA00FA00EA10"
    )
    port map (
      ADR4 => NlwRenamedSig_OI_counter_value(0),
      ADR0 => ud,
      ADR1 => NlwRenamedSig_OI_counter_value(1),
      ADR3 => NlwRenamedSig_OI_counter_value(3),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      ADR2 => count,
      O => counter_value_int_mux0001(3)
    );
  counter_value_int_2 : X_FF
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(4),
      O => NlwRenamedSig_OI_counter_value(2),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_4_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => X"7E817E81F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => NlwRenamedSig_OI_counter_value(0),
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(2),
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR5 => count,
      O => counter_value_int_mux0001(4)
    );
  counter_value_int_1 : X_FF
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(5),
      O => NlwRenamedSig_OI_counter_value(1),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_5_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => X"6699CC006699CC00"
    )
    port map (
      ADR5 => VCC,
      ADR2 => VCC,
      ADR1 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(1),
      ADR0 => NlwRenamedSig_OI_counter_value(0),
      ADR4 => count,
      O => counter_value_int_mux0001(5)
    );
  counter_value_int_0 : X_FF
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(6),
      O => NlwRenamedSig_OI_counter_value(0),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_6_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y74",
      INIT => X"44AA44AA44AA44AA"
    )
    port map (
      ADR4 => VCC,
      ADR5 => VCC,
      ADR2 => VCC,
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR0 => count,
      ADR1 => ud,
      O => counter_value_int_mux0001(6)
    );
  counter_value_int_mux0001_2_Q : X_MUX2
    generic map(
      LOC => "SLICE_X106Y75"
    )
    port map (
      IA => N22,
      IB => N31,
      O => counter_value_int_mux0001(2),
      SEL => ud
    );
  counter_value_int_mux0001_2_F : X_LUT6
    generic map(
      LOC => "SLICE_X106Y75",
      INIT => X"F0F00000F0E00010"
    )
    port map (
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR2 => count,
      ADR4 => NlwRenamedSig_OI_counter_value(4),
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      O => N22
    );
  counter_value_int_4 : X_FF
    generic map(
      LOC => "SLICE_X106Y75",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(2),
      O => NlwRenamedSig_OI_counter_value(4),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_2_G : X_LUT6
    generic map(
      LOC => "SLICE_X106Y75",
      INIT => X"7FFF8000FFFF0000"
    )
    port map (
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      ADR2 => count,
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR4 => NlwRenamedSig_OI_counter_value(4),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      O => N31
    );
  counter_value_int_6 : X_FF
    generic map(
      LOC => "SLICE_X107Y75",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(0),
      O => NlwRenamedSig_OI_counter_value(6),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_0_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y75",
      INIT => X"7C80EC107C80EC10"
    )
    port map (
      ADR5 => VCC,
      ADR0 => NlwRenamedSig_OI_counter_value(5),
      ADR1 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(6),
      ADR4 => Maddsub_counter_value_int_addsub0000_cy(4),
      ADR2 => count,
      O => counter_value_int_mux0001(0)
    );
  counter_value_int_5 : X_FF
    generic map(
      LOC => "SLICE_X107Y75",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(1),
      O => NlwRenamedSig_OI_counter_value(5),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_1_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y75",
      INIT => X"33CCCC00CC33CC00"
    )
    port map (
      ADR0 => VCC,
      ADR2 => VCC,
      ADR1 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(5),
      ADR5 => Maddsub_counter_value_int_addsub0000_cy(4),
      ADR4 => count,
      O => counter_value_int_mux0001(1)
    );
  Maddsub_counter_value_int_addsub0000_cy_4_11 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y75",
      INIT => X"88FE888800FE0000"
    )
    port map (
      ADR4 => count,
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      ADR3 => ud,
      ADR2 => N21,
      ADR0 => NlwRenamedSig_OI_counter_value(4),
      ADR5 => N23,
      O => Maddsub_counter_value_int_addsub0000_cy(4)
    );
  Maddsub_counter_value_int_addsub0000_cy_4_121 : X_LUT6
    generic map(
      LOC => "SLICE_X108Y75",
      INIT => X"CCCC000000000000"
    )
    port map (
      ADR0 => VCC,
      ADR3 => VCC,
      ADR2 => VCC,
      ADR1 => NlwRenamedSig_OI_counter_value(1),
      ADR4 => NlwRenamedSig_OI_counter_value(0),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      O => N23
    );
  counter_value_int_mux0001_3_11 : X_LUT6
    generic map(
      LOC => "SLICE_X109Y75",
      INIT => X"FFFFFFFFFFFFCCCC"
    )
    port map (
      ADR0 => VCC,
      ADR3 => VCC,
      ADR2 => VCC,
      ADR4 => NlwRenamedSig_OI_counter_value(0),
      ADR1 => NlwRenamedSig_OI_counter_value(1),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      O => N21
    );
  NlwBlock_machine_counter_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_machine_counter_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity BIT_ALIGN_MACHINE is
  port (
    RXCLKDIV : in STD_LOGIC := 'X'; 
    RST : in STD_LOGIC := 'X'; 
    SAP : in STD_LOGIC := 'X'; 
    USE_BITSLIP : in STD_LOGIC := 'X'; 
    BITSLIP : out STD_LOGIC; 
    ICE : out STD_LOGIC; 
    INC : out STD_LOGIC; 
    DATA_ALIGNED : out STD_LOGIC; 
    RXDATA : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end BIT_ALIGN_MACHINE;

architecture Structure of BIT_ALIGN_MACHINE is
  component count_to_128_INST_1
    port (
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      ud : in STD_LOGIC := 'X'; 
      count : in STD_LOGIC := 'X'; 
      counter_value : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
    );
  end component;
  component count_to_128_INST_2
    port (
      clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      ud : in STD_LOGIC := 'X'; 
      count : in STD_LOGIC := 'X'; 
      counter_value : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
    );
  end component;
  component seven_bit_reg_w_ce
    port (
      CLK : in STD_LOGIC := 'X'; 
      CE : in STD_LOGIC := 'X'; 
      RST : in STD_LOGIC := 'X'; 
      D : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
      Q : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
    );
  end component;
  signal UD : STD_LOGIC; 
  signal COUNT : STD_LOGIC; 
  signal COUNT_SAMPLE : STD_LOGIC; 
  signal STORE : STD_LOGIC; 
  signal STORE_DATA_PREV : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In55_4391 : STD_LOGIC; 
  signal N20 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_4393 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In10_4394 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_4395 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal CURRENT_STATE_cmp_lt00021_4397 : STD_LOGIC; 
  signal CURRENT_STATE_cmp_lt00022_4398 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In128_4401 : STD_LOGIC; 
  signal CURRENT_STATE_cmp_ne0000_4402 : STD_LOGIC; 
  signal CURRENT_STATE_cmp_lt0001 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd3_4405 : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd2_In95_4407 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd2_4408 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd1_4409 : STD_LOGIC; 
  signal N26 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In92_4413 : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In188_4415 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In143_4416 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In250_4417 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In228_4418 : STD_LOGIC; 
  signal N17 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In36_4420 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In127_4421 : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In82_4423 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In44_4425 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In107_4426 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In289_4427 : STD_LOGIC; 
  signal N171 : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In48_4430 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In244_4431 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd2_In116_4432 : STD_LOGIC; 
  signal DATA_ALIGNEDx : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd5_In : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd4_In : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd1_In : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd3_In_4111 : STD_LOGIC; 
  signal N201 : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal CURRENT_STATE_FSM_FFd2_In : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal COUNT_VALUE : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal COUNT_VALUE_SAMPLE : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal CVS : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RXDATA_PREV : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal CURRENT_STATE_addsub0000 : STD_LOGIC_VECTOR ( 5 downto 4 ); 
begin
  machine_counter : count_to_128_INST_1
    port map (
      clk => RXCLKDIV,
      rst => RST,
      ud => UD,
      count => COUNT,
      counter_value(6) => COUNT_VALUE(6),
      counter_value(5) => COUNT_VALUE(5),
      counter_value(4) => COUNT_VALUE(4),
      counter_value(3) => COUNT_VALUE(3),
      counter_value(2) => COUNT_VALUE(2),
      counter_value(1) => COUNT_VALUE(1),
      counter_value(0) => COUNT_VALUE(0)
    );
  machine_counter_total : count_to_128_INST_2
    port map (
      clk => RXCLKDIV,
      rst => RST,
      ud => COUNT_SAMPLE,
      count => COUNT_SAMPLE,
      counter_value(6) => COUNT_VALUE_SAMPLE(6),
      counter_value(5) => COUNT_VALUE_SAMPLE(5),
      counter_value(4) => COUNT_VALUE_SAMPLE(4),
      counter_value(3) => COUNT_VALUE_SAMPLE(3),
      counter_value(2) => COUNT_VALUE_SAMPLE(2),
      counter_value(1) => COUNT_VALUE_SAMPLE(1),
      counter_value(0) => COUNT_VALUE_SAMPLE(0)
    );
  tap_reserve : seven_bit_reg_w_ce
    port map (
      CLK => RXCLKDIV,
      CE => STORE,
      RST => RST,
      D(6) => COUNT_VALUE(6),
      D(5) => COUNT_VALUE(5),
      D(4) => COUNT_VALUE(4),
      D(3) => COUNT_VALUE(3),
      D(2) => COUNT_VALUE(2),
      D(1) => COUNT_VALUE(1),
      D(0) => COUNT_VALUE(0),
      Q(6) => CVS(6),
      Q(5) => CVS(5),
      Q(4) => CVS(4),
      Q(3) => CVS(3),
      Q(2) => CVS(2),
      Q(1) => CVS(1),
      Q(0) => CVS(0)
    );
  Msub_CURRENT_STATE_addsub0000_xor_4_11 : X_LUT6
    generic map(
      LOC => "SLICE_X102Y65",
      INIT => X"FFFEFFFE00010001"
    )
    port map (
      ADR4 => VCC,
      ADR0 => CVS(1),
      ADR5 => CVS(5),
      ADR2 => CVS(2),
      ADR3 => CVS(3),
      ADR1 => CVS(4),
      O => CURRENT_STATE_addsub0000(4)
    );
  Msub_CURRENT_STATE_addsub0000_xor_5_11 : X_LUT6
    generic map(
      LOC => "SLICE_X102Y66",
      INIT => X"F0F0F0F0F0F0F0E1"
    )
    port map (
      ADR1 => CVS(1),
      ADR2 => CVS(6),
      ADR4 => CVS(2),
      ADR5 => CVS(3),
      ADR0 => CVS(4),
      ADR3 => CVS(5),
      O => CURRENT_STATE_addsub0000(5)
    );
  CURRENT_STATE_FSM_FFd5_In22_SW0 : X_LUT6
    generic map(
      LOC => "SLICE_X102Y66",
      INIT => X"FFFFFFFF00FF00FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR4 => VCC,
      ADR3 => CVS(0),
      ADR5 => CVS(1),
      O => N21
    );
  CURRENT_STATE_FSM_FFd5_In22 : X_LUT6
    generic map(
      LOC => "SLICE_X102Y66",
      INIT => X"FFFFFFFFFFFFFFFE"
    )
    port map (
      ADR3 => CVS(6),
      ADR1 => CVS(5),
      ADR5 => CVS(4),
      ADR0 => CVS(3),
      ADR2 => CVS(2),
      ADR4 => N21,
      O => N17
    );
  CURRENT_STATE_FSM_Out11 : X_LUT6