lvds_bist_top_timesim.vhd

FPGA之间的LVDS传输

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.37
--  \   \         Application: netgen
--  /   /         Filename: lvds_bist_top_timesim.vhd
-- /___/   /\     Timestamp: Mon Nov 03 11:34:29 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 1 -pcf lvds_bist_top.pcf -rpw 100 -tpw 0 -ar Structure -tm lvds_bist_top -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim lvds_bist_top.ncd lvds_bist_top_timesim.vhd 
-- Device	: 5vfx100tff1738-1 (ADVANCED 1.61 2008-05-28)
-- Input file	: lvds_bist_top.ncd
-- Output file	: F:\LAB\LVDS\LVDS_4to1-rx-AMC-v1.0\netgen\par\lvds_bist_top_timesim.vhd
-- # of Entities	: 14
-- Design Name	: lvds_bist_top
-- Xilinx	: E:\Xilinx10\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity seven_bit_reg_w_ce is
  port (
    CLK : in STD_LOGIC := 'X'; 
    CE : in STD_LOGIC := 'X'; 
    RST : in STD_LOGIC := 'X'; 
    D : in STD_LOGIC_VECTOR ( 6 downto 0 ); 
    Q : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end seven_bit_reg_w_ce;

architecture Structure of seven_bit_reg_w_ce is
  signal GND : STD_LOGIC; 
begin
  bit6 : X_SFF
    generic map(
      LOC => "SLICE_X102Y68",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(6),
      O => Q(6),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit5 : X_SFF
    generic map(
      LOC => "SLICE_X102Y68",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(5),
      O => Q(5),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit4 : X_SFF
    generic map(
      LOC => "SLICE_X102Y68",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(4),
      O => Q(4),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit3 : X_SFF
    generic map(
      LOC => "SLICE_X103Y66",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(3),
      O => Q(3),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit2 : X_SFF
    generic map(
      LOC => "SLICE_X103Y66",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(2),
      O => Q(2),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit1 : X_SFF
    generic map(
      LOC => "SLICE_X103Y66",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(1),
      O => Q(1),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  bit0 : X_SFF
    generic map(
      LOC => "SLICE_X103Y66",
      INIT => '0'
    )
    port map (
      CE => CE,
      CLK => CLK,
      I => D(0),
      O => Q(0),
      SSET => GND,
      SRST => RST,
      SET => GND,
      RST => GND
    );
  NlwBlock_tap_reserve_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity count_to_128_INST_2 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    ud : in STD_LOGIC := 'X'; 
    count : in STD_LOGIC := 'X'; 
    counter_value : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end count_to_128_INST_2;

architecture Structure of count_to_128_INST_2 is
  signal N21 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwRenamedSig_OI_counter_value : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 4 downto 4 ); 
  signal counter_value_int_mux0001 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
begin
  counter_value(6) <= NlwRenamedSig_OI_counter_value(6);
  counter_value(5) <= NlwRenamedSig_OI_counter_value(5);
  counter_value(4) <= NlwRenamedSig_OI_counter_value(4);
  counter_value(3) <= NlwRenamedSig_OI_counter_value(3);
  counter_value(2) <= NlwRenamedSig_OI_counter_value(2);
  counter_value(1) <= NlwRenamedSig_OI_counter_value(1);
  counter_value(0) <= NlwRenamedSig_OI_counter_value(0);
  counter_value_int_3 : X_FF
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(3),
      O => NlwRenamedSig_OI_counter_value(3),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_3_2 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => X"7FFE8001CCCC0000"
    )
    port map (
      ADR2 => NlwRenamedSig_OI_counter_value(0),
      ADR1 => ud,
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR4 => NlwRenamedSig_OI_counter_value(3),
      ADR3 => NlwRenamedSig_OI_counter_value(2),
      ADR5 => ud,
      O => counter_value_int_mux0001(3)
    );
  counter_value_int_2 : X_FF
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(4),
      O => NlwRenamedSig_OI_counter_value(2),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_4_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => X"7E817E81F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => NlwRenamedSig_OI_counter_value(0),
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(2),
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR5 => ud,
      O => counter_value_int_mux0001(4)
    );
  counter_value_int_1 : X_FF
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(5),
      O => NlwRenamedSig_OI_counter_value(1),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_5_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => X"5AA55AA5F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => VCC,
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(1),
      ADR0 => NlwRenamedSig_OI_counter_value(0),
      ADR5 => ud,
      O => counter_value_int_mux0001(5)
    );
  counter_value_int_0 : X_FF
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(6),
      O => NlwRenamedSig_OI_counter_value(0),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_6_1 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y66",
      INIT => X"00FFFF0000FF0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR4 => ud,
      ADR5 => ud,
      O => counter_value_int_mux0001(6)
    );
  Maddsub_counter_value_int_addsub0000_cy_4_121 : X_LUT6
    generic map(
      LOC => "SLICE_X106Y67",
      INIT => X"C0C00000C0C00000"
    )
    port map (
      ADR0 => VCC,
      ADR3 => VCC,
      ADR5 => VCC,
      ADR4 => NlwRenamedSig_OI_counter_value(1),
      ADR1 => NlwRenamedSig_OI_counter_value(0),
      ADR2 => NlwRenamedSig_OI_counter_value(2),
      O => N23
    );
  counter_value_int_mux0001_3_11 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y66",
      INIT => X"FFEEFFEEFFEEFFEE"
    )
    port map (
      ADR4 => VCC,
      ADR5 => VCC,
      ADR2 => VCC,
      ADR1 => NlwRenamedSig_OI_counter_value(0),
      ADR0 => NlwRenamedSig_OI_counter_value(1),
      ADR3 => NlwRenamedSig_OI_counter_value(2),
      O => N21
    );
  counter_value_int_6 : X_FF
    generic map(
      LOC => "SLICE_X107Y67",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(0),
      O => NlwRenamedSig_OI_counter_value(6),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_0_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y67",
      INIT => X"5FA0FA05F000F000"
    )
    port map (
      ADR1 => VCC,
      ADR0 => NlwRenamedSig_OI_counter_value(5),
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(6),
      ADR4 => Maddsub_counter_value_int_addsub0000_cy(4),
      ADR5 => ud,
      O => counter_value_int_mux0001(0)
    );
  counter_value_int_5 : X_FF
    generic map(
      LOC => "SLICE_X107Y67",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(1),
      O => NlwRenamedSig_OI_counter_value(5),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_1_1 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y67",
      INIT => X"5AA55AA5F000F000"
    )
    port map (
      ADR4 => VCC,
      ADR1 => VCC,
      ADR2 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(5),
      ADR0 => Maddsub_counter_value_int_addsub0000_cy(4),
      ADR5 => ud,
      O => counter_value_int_mux0001(1)
    );
  Maddsub_counter_value_int_addsub0000_cy_4_11 : X_LUT6
    generic map(
      LOC => "SLICE_X107Y67",
      INIT => X"CE0A0A0ACE080A08"
    )
    port map (
      ADR0 => ud,
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      ADR2 => ud,
      ADR5 => N21,
      ADR3 => NlwRenamedSig_OI_counter_value(4),
      ADR4 => N23,
      O => Maddsub_counter_value_int_addsub0000_cy(4)
    );
  counter_value_int_mux0001_2_Q : X_MUX2
    generic map(
      LOC => "SLICE_X107Y68"
    )
    port map (
      IA => N22,
      IB => N31,
      O => counter_value_int_mux0001(2),
      SEL => ud
    );
  counter_value_int_mux0001_2_F : X_LUT6
    generic map(
      LOC => "SLICE_X107Y68",
      INIT => X"AAAAAAA900000000"
    )
    port map (
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR5 => ud,
      ADR0 => NlwRenamedSig_OI_counter_value(4),
      ADR2 => NlwRenamedSig_OI_counter_value(1),
      ADR4 => NlwRenamedSig_OI_counter_value(2),
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      O => N22
    );
  counter_value_int_4 : X_FF
    generic map(
      LOC => "SLICE_X107Y68",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => clk,
      I => counter_value_int_mux0001(2),
      O => NlwRenamedSig_OI_counter_value(4),
      SET => GND,
      RST => rst
    );
  counter_value_int_mux0001_2_G : X_LUT6
    generic map(
      LOC => "SLICE_X107Y68",
      INIT => X"6AAAAAAAAAAAAAAA"
    )
    port map (
      ADR1 => NlwRenamedSig_OI_counter_value(3),
      ADR4 => ud,
      ADR3 => NlwRenamedSig_OI_counter_value(0),
      ADR0 => NlwRenamedSig_OI_counter_value(4),
      ADR5 => NlwRenamedSig_OI_counter_value(2),
      ADR2 => NlwRenamedSig_OI_counter_value(1),
      O => N31
    );
  NlwBlock_machine_counter_total_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_machine_counter_total_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity count_to_128_INST_1 is
  port (
    clk : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    ud : in STD_LOGIC := 'X'; 
    count : in STD_LOGIC := 'X'; 
    counter_value : out STD_LOGIC_VECTOR ( 6 downto 0 ) 
  );
end count_to_128_INST_1;

architecture Structure of count_to_128_INST_1 is
  signal N21 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N22 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal VCC : STD_LOGIC;