lvds_tx_rx_merge_timesim.nlf

FPGA之间的LVDS传输

Release 10.1.02 - netgen K.37 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 1 -pcf lvds_tx_rx_merge.pcf -rpw 100 -tpw
0 -ar Structure -tm lvds_tx_rx_merge -insert_pp_buffers false -w -dir netgen/par
-ofmt vhdl -sim lvds_tx_rx_merge.ncd lvds_tx_rx_merge_timesim.vhd  

Read and Annotate design 'lvds_tx_rx_merge.ncd' ...
Loading device for application Rf_Device from file '5vsx50t.nph' in environment
K:\Xilinx\10.1\ISE.
   "lvds_tx_rx_merge" is an NCD, version 3.2, device xc5vsx50t, package ff1136,
speed -1
Loading constraints from 'lvds_tx_rx_merge.pcf'...
The speed grade (-1) differs from the speed grade specified in the .ncd file
(-1).
The number of routable networks is 1634
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist
'E:\ISEworks\LVDS\LVDS_4to1\netgen\par\lvds_tx_rx_merge_timesim.vhd' ...
Writing VHDL SDF file
'E:\ISEworks\LVDS\LVDS_4to1\netgen\par\lvds_tx_rx_merge_timesim.sdf' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. 
INFO:NetListWriters - Setup Simulation - To perform a setup simulation, specify
   values in the Maximum (MAX) field with the following command line modifier: 
   -SDFMAX
INFO:NetListWriters - Hold Simulation - To perform the most accurate hold
   simulation, specify values in the Minimum (MIN) field with the following
   command line modifier:  -SDFMIN
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
   to the simulator, see your Simulator tool documentation.
Number of warnings: 0
Number of info messages: 4
Total memory usage is 282104 kilobytes