ddr_6to1_16chan_rt_tx_timesim.vhd

FPGA之间的LVDS传输

  OSERDES_TX_DATA_10_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(61),
      O => OSERDES_TX_DATA_10_D2_INT
    );
  OSERDES_TX_DATA_10_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(60),
      O => OSERDES_TX_DATA_10_D1_INT
    );
  OSERDES_TX_DATA_10 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y123"
    )
    port map (
      D1 => OSERDES_TX_DATA_10_D1_INT,
      D2 => OSERDES_TX_DATA_10_D2_INT,
      D3 => OSERDES_TX_DATA_10_D3_INT,
      D4 => OSERDES_TX_DATA_10_D4_INT,
      D5 => OSERDES_TX_DATA_10_D5_INT,
      D6 => OSERDES_TX_DATA_10_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC0,
      T4 => GLOBAL_LOGIC0,
      CLK => OSERDES_TX_DATA_10_CLK_INT,
      OCE => GLOBAL_LOGIC1,
      TCE => GLOBAL_LOGIC0,
      SR => RESET_IBUF_1110,
      REV => GLOBAL_LOGIC0,
      CLKDIV => OSERDES_TX_DATA_10_CLKDIV_INT,
      SHIFTIN1 => GND,
      SHIFTIN2 => GND,
      OQ => TX_DATA_PREBUF(10),
      TQ => OSERDES_TX_DATA_10_TQ,
      SHIFTOUT1 => OSERDES_TX_DATA_10_SHIFTOUT1,
      SHIFTOUT2 => OSERDES_TX_DATA_10_SHIFTOUT2
    );
  OSERDES_TX_DATA_02_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_02_CLKDIV_INT
    );
  OSERDES_TX_DATA_02_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_02_CLK_INT
    );
  OSERDES_TX_DATA_02_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(17),
      O => OSERDES_TX_DATA_02_D6_INT
    );
  OSERDES_TX_DATA_02_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(16),
      O => OSERDES_TX_DATA_02_D5_INT
    );
  OSERDES_TX_DATA_02_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(15),
      O => OSERDES_TX_DATA_02_D4_INT
    );
  OSERDES_TX_DATA_02_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(14),
      O => OSERDES_TX_DATA_02_D3_INT
    );
  OSERDES_TX_DATA_02_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(13),
      O => OSERDES_TX_DATA_02_D2_INT
    );
  OSERDES_TX_DATA_02_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y113",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(12),
      O => OSERDES_TX_DATA_02_D1_INT
    );
  OSERDES_TX_DATA_02 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y113"
    )
    port map (
      D1 => OSERDES_TX_DATA_02_D1_INT,
      D2 => OSERDES_TX_DATA_02_D2_INT,
      D3 => OSERDES_TX_DATA_02_D3_INT,
      D4 => OSERDES_TX_DATA_02_D4_INT,
      D5 => OSERDES_TX_DATA_02_D5_INT,
      D6 => OSERDES_TX_DATA_02_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC0,
      T4 => GLOBAL_LOGIC0,
      CLK => OSERDES_TX_DATA_02_CLK_INT,
      OCE => GLOBAL_LOGIC1,
      TCE => GLOBAL_LOGIC0,
      SR => RESET_IBUF_1110,
      REV => GLOBAL_LOGIC0,
      CLKDIV => OSERDES_TX_DATA_02_CLKDIV_INT,
      SHIFTIN1 => GND,
      SHIFTIN2 => GND,
      OQ => TX_DATA_PREBUF(2),
      TQ => OSERDES_TX_DATA_02_TQ,
      SHIFTOUT1 => OSERDES_TX_DATA_02_SHIFTOUT1,
      SHIFTOUT2 => OSERDES_TX_DATA_02_SHIFTOUT2
    );
  OSERDES_TX_DATA_11_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_11_CLKDIV_INT
    );
  OSERDES_TX_DATA_11_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_11_CLK_INT
    );
  OSERDES_TX_DATA_11_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(71),
      O => OSERDES_TX_DATA_11_D6_INT
    );
  OSERDES_TX_DATA_11_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(70),
      O => OSERDES_TX_DATA_11_D5_INT
    );
  OSERDES_TX_DATA_11_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(69),
      O => OSERDES_TX_DATA_11_D4_INT
    );
  OSERDES_TX_DATA_11_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(68),
      O => OSERDES_TX_DATA_11_D3_INT
    );
  OSERDES_TX_DATA_11_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(67),
      O => OSERDES_TX_DATA_11_D2_INT
    );
  OSERDES_TX_DATA_11_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y97",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(66),
      O => OSERDES_TX_DATA_11_D1_INT
    );
  OSERDES_TX_DATA_11 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y97"
    )
    port map (
      D1 => OSERDES_TX_DATA_11_D1_INT,
      D2 => OSERDES_TX_DATA_11_D2_INT,
      D3 => OSERDES_TX_DATA_11_D3_INT,
      D4 => OSERDES_TX_DATA_11_D4_INT,
      D5 => OSERDES_TX_DATA_11_D5_INT,
      D6 => OSERDES_TX_DATA_11_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC0,
      T4 => GLOBAL_LOGIC0,
      CLK => OSERDES_TX_DATA_11_CLK_INT,
      OCE => GLOBAL_LOGIC1,
      TCE => GLOBAL_LOGIC0,
      SR => RESET_IBUF_1110,
      REV => GLOBAL_LOGIC0,
      CLKDIV => OSERDES_TX_DATA_11_CLKDIV_INT,
      SHIFTIN1 => GND,
      SHIFTIN2 => GND,
      OQ => TX_DATA_PREBUF(11),
      TQ => OSERDES_TX_DATA_11_TQ,
      SHIFTOUT1 => OSERDES_TX_DATA_11_SHIFTOUT1,
      SHIFTOUT2 => OSERDES_TX_DATA_11_SHIFTOUT2
    );
  OSERDES_TX_DATA_03_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_03_CLKDIV_INT
    );
  OSERDES_TX_DATA_03_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_03_CLK_INT
    );
  OSERDES_TX_DATA_03_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(23),
      O => OSERDES_TX_DATA_03_D6_INT
    );
  OSERDES_TX_DATA_03_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(22),
      O => OSERDES_TX_DATA_03_D5_INT
    );
  OSERDES_TX_DATA_03_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(21),
      O => OSERDES_TX_DATA_03_D4_INT
    );
  OSERDES_TX_DATA_03_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(20),
      O => OSERDES_TX_DATA_03_D3_INT
    );
  OSERDES_TX_DATA_03_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(19),
      O => OSERDES_TX_DATA_03_D2_INT
    );
  OSERDES_TX_DATA_03_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y115",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(18),
      O => OSERDES_TX_DATA_03_D1_INT
    );
  OSERDES_TX_DATA_03 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y115"
    )
    port map (
      D1 => OSERDES_TX_DATA_03_D1_INT,
      D2 => OSERDES_TX_DATA_03_D2_INT,
      D3 => OSERDES_TX_DATA_03_D3_INT,
      D4 => OSERDES_TX_DATA_03_D4_INT,
      D5 => OSERDES_TX_DATA_03_D5_INT,
      D6 => OSERDES_TX_DATA_03_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC0,
      T4 => GLOBAL_LOGIC0,
      CLK => OSERDES_TX_DATA_03_CLK_INT,
      OCE => GLOBAL_LOGIC1,
      TCE => GLOBAL_LOGIC0,
      SR => RESET_IBUF_1110,
      REV => GLOBAL_LOGIC0,
      CLKDIV => OSERDES_TX_DATA_03_CLKDIV_INT,
      SHIFTIN1 => GND,
      SHIFTIN2 => GND,
      OQ => TX_DATA_PREBUF(3),
      TQ => OSERDES_TX_DATA_03_TQ,
      SHIFTOUT1 => OSERDES_TX_DATA_03_SHIFTOUT1,
      SHIFTOUT2 => OSERDES_TX_DATA_03_SHIFTOUT2
    );
  OSERDES_TX_DATA_12_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_12_CLKDIV_INT
    );
  OSERDES_TX_DATA_12_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_12_CLK_INT
    );
  OSERDES_TX_DATA_12_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(77),
      O => OSERDES_TX_DATA_12_D6_INT
    );
  OSERDES_TX_DATA_12_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(76),
      O => OSERDES_TX_DATA_12_D5_INT
    );
  OSERDES_TX_DATA_12_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(75),
      O => OSERDES_TX_DATA_12_D4_INT
    );
  OSERDES_TX_DATA_12_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(74),
      O => OSERDES_TX_DATA_12_D3_INT
    );
  OSERDES_TX_DATA_12_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(73),
      O => OSERDES_TX_DATA_12_D2_INT
    );
  OSERDES_TX_DATA_12_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y109",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(72),
      O => OSERDES_TX_DATA_12_D1_INT
    );
  OSERDES_TX_DATA_12 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y109"
    )
    port map (
      D1 => OSERDES_TX_DATA_12_D1_INT,
      D2 => OSERDES_TX_DATA_12_D2_INT,
      D3 => OSERDES_TX_DATA_12_D3_INT,
      D4 => OSERDES_TX_DATA_12_D4_INT,
      D5 => OSERDES_TX_DATA_12_D5_INT,
      D6 => OSERDES_TX_DATA_12_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC