ddr_6to1_16chan_rt_tx_timesim.vhd

FPGA之间的LVDS传输

      OB => DATA_TX_N(5)
    );
  OBUFDS_TX_DATA_06_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y119"
    )
    port map (
      I => TX_DATA_PREBUF(6),
      O => DATA_TX_P(6),
      OB => DATA_TX_N(6)
    );
  OBUFDS_TX_DATA_07_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y103"
    )
    port map (
      I => TX_DATA_PREBUF(7),
      O => DATA_TX_P(7),
      OB => DATA_TX_N(7)
    );
  TXCLKDIV_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "IOB_X1Y167",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV,
      O => TXCLKDIV_INBUF_B
    );
  OBUFDS_TX_DATA_08_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y121"
    )
    port map (
      I => TX_DATA_PREBUF(8),
      O => DATA_TX_P(8),
      OB => DATA_TX_N(8)
    );
  OBUFDS_TX_DATA_09_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y105"
    )
    port map (
      I => TX_DATA_PREBUF(9),
      O => DATA_TX_P(9),
      OB => DATA_TX_N(9)
    );
  OBUFDS_TX_CLOCK_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y223"
    )
    port map (
      I => TX_CLOCK_PREBUF,
      O => CLOCK_TX_P,
      OB => CLOCK_TX_N
    );
  DATA_TO_OSERDES_10_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y177",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(10),
      O => DATA_TO_OSERDES_10_INBUF_B
    );
  DATA_TO_OSERDES_11_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y95",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(11),
      O => DATA_TO_OSERDES_11_INBUF_B
    );
  DATA_TO_OSERDES_20_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y128",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(20),
      O => DATA_TO_OSERDES_20_INBUF_B
    );
  DATA_TO_OSERDES_12_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y171",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(12),
      O => DATA_TO_OSERDES_12_INBUF_B
    );
  DATA_TO_OSERDES_21_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y88",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(21),
      O => DATA_TO_OSERDES_21_INBUF_B
    );
  DATA_TO_OSERDES_0_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y168",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(0),
      O => DATA_TO_OSERDES_0_INBUF_B
    );
  DATA_TO_OSERDES_1_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y169",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(1),
      O => DATA_TO_OSERDES_1_INBUF_B
    );
  DATA_TO_OSERDES_2_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y85",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(2),
      O => DATA_TO_OSERDES_2_INBUF_B
    );
  TXCLK_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "IOB_X1Y61",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK,
      O => TXCLK_INBUF_B
    );
  DATA_TO_OSERDES_3_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y92",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(3),
      O => DATA_TO_OSERDES_3_INBUF_B
    );
  DATA_TO_OSERDES_4_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y172",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(4),
      O => DATA_TO_OSERDES_4_INBUF_B
    );
  DATA_TO_OSERDES_5_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y91",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(5),
      O => DATA_TO_OSERDES_5_INBUF_B
    );
  DATA_TO_OSERDES_6_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y170",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(6),
      O => DATA_TO_OSERDES_6_INBUF_B
    );
  DATA_TO_OSERDES_7_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y166",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(7),
      O => DATA_TO_OSERDES_7_INBUF_B
    );
  OBUFDS_TX_DATA_00_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y107"
    )
    port map (
      I => TX_DATA_PREBUF(0),
      O => DATA_TX_P(0),
      OB => DATA_TX_N(0)
    );
  DATA_TO_OSERDES_8_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y90",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(8),
      O => DATA_TO_OSERDES_8_INBUF_B
    );
  OBUFDS_TX_DATA_01_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y111"
    )
    port map (
      I => TX_DATA_PREBUF(1),
      O => DATA_TX_P(1),
      OB => DATA_TX_N(1)
    );
  OSERDES_TX_DATA_00_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_00_CLKDIV_INT
    );
  OSERDES_TX_DATA_00_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_00_CLK_INT
    );
  OSERDES_TX_DATA_00_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(5),
      O => OSERDES_TX_DATA_00_D6_INT
    );
  OSERDES_TX_DATA_00_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(4),
      O => OSERDES_TX_DATA_00_D5_INT
    );
  OSERDES_TX_DATA_00_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(3),
      O => OSERDES_TX_DATA_00_D4_INT
    );
  OSERDES_TX_DATA_00_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(2),
      O => OSERDES_TX_DATA_00_D3_INT
    );
  OSERDES_TX_DATA_00_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(1),
      O => OSERDES_TX_DATA_00_D2_INT
    );
  OSERDES_TX_DATA_00_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y107",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(0),
      O => OSERDES_TX_DATA_00_D1_INT
    );
  OSERDES_TX_DATA_00 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y107"
    )
    port map (
      D1 => OSERDES_TX_DATA_00_D1_INT,
      D2 => OSERDES_TX_DATA_00_D2_INT,
      D3 => OSERDES_TX_DATA_00_D3_INT,
      D4 => OSERDES_TX_DATA_00_D4_INT,
      D5 => OSERDES_TX_DATA_00_D5_INT,
      D6 => OSERDES_TX_DATA_00_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC0,
      T4 => GLOBAL_LOGIC0,
      CLK => OSERDES_TX_DATA_00_CLK_INT,
      OCE => GLOBAL_LOGIC1,
      TCE => GLOBAL_LOGIC0,
      SR => RESET_IBUF_1110,
      REV => GLOBAL_LOGIC0,
      CLKDIV => OSERDES_TX_DATA_00_CLKDIV_INT,
      SHIFTIN1 => GND,
      SHIFTIN2 => GND,
      OQ => TX_DATA_PREBUF(0),
      TQ => OSERDES_TX_DATA_00_TQ,
      SHIFTOUT1 => OSERDES_TX_DATA_00_SHIFTOUT1,
      SHIFTOUT2 => OSERDES_TX_DATA_00_SHIFTOUT2
    );
  OSERDES_TX_DATA_01_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_01_CLKDIV_INT
    );
  OSERDES_TX_DATA_01_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_01_CLK_INT
    );
  OSERDES_TX_DATA_01_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(11),
      O => OSERDES_TX_DATA_01_D6_INT
    );
  OSERDES_TX_DATA_01_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(10),
      O => OSERDES_TX_DATA_01_D5_INT
    );
  OSERDES_TX_DATA_01_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(9),
      O => OSERDES_TX_DATA_01_D4_INT
    );
  OSERDES_TX_DATA_01_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(8),
      O => OSERDES_TX_DATA_01_D3_INT
    );
  OSERDES_TX_DATA_01_D2INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(7),
      O => OSERDES_TX_DATA_01_D2_INT
    );
  OSERDES_TX_DATA_01_D1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y111",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(6),
      O => OSERDES_TX_DATA_01_D1_INT
    );
  OSERDES_TX_DATA_01 : X_OSERDES
    generic map(
      SERDES_MODE => "MASTER",
      DATA_RATE_OQ => "DDR",
      DATA_RATE_TQ => "DDR",
      DATA_WIDTH => 6,
      TRISTATE_WIDTH => 1,
      INIT_OQ => '0',
      INIT_TQ => '0',
      SRVAL_OQ => '0',
      SRVAL_TQ => '0',
      LOC => "OLOGIC_X0Y111"
    )
    port map (
      D1 => OSERDES_TX_DATA_01_D1_INT,
      D2 => OSERDES_TX_DATA_01_D2_INT,
      D3 => OSERDES_TX_DATA_01_D3_INT,
      D4 => OSERDES_TX_DATA_01_D4_INT,
      D5 => OSERDES_TX_DATA_01_D5_INT,
      D6 => OSERDES_TX_DATA_01_D6_INT,
      T1 => GLOBAL_LOGIC0,
      T2 => GLOBAL_LOGIC0,
      T3 => GLOBAL_LOGIC0,
      T4 => GLOBAL_LOGIC0,
      CLK => OSERDES_TX_DATA_01_CLK_INT,
      OCE => GLOBAL_LOGIC1,
      TCE => GLOBAL_LOGIC0,
      SR => RESET_IBUF_1110,
      REV => GLOBAL_LOGIC0,
      CLKDIV => OSERDES_TX_DATA_01_CLKDIV_INT,
      SHIFTIN1 => GND,
      SHIFTIN2 => GND,
      OQ => TX_DATA_PREBUF(1),
      TQ => OSERDES_TX_DATA_01_TQ,
      SHIFTOUT1 => OSERDES_TX_DATA_01_SHIFTOUT1,
      SHIFTOUT2 => OSERDES_TX_DATA_01_SHIFTOUT2
    );
  OSERDES_TX_DATA_10_CLKDIVINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLKDIV_BUFGP,
      O => OSERDES_TX_DATA_10_CLKDIV_INT
    );
  OSERDES_TX_DATA_10_CLKINV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => OSERDES_TX_DATA_10_CLK_INT
    );
  OSERDES_TX_DATA_10_D6INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(65),
      O => OSERDES_TX_DATA_10_D6_INT
    );
  OSERDES_TX_DATA_10_D5INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(64),
      O => OSERDES_TX_DATA_10_D5_INT
    );
  OSERDES_TX_DATA_10_D4INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(63),
      O => OSERDES_TX_DATA_10_D4_INT
    );
  OSERDES_TX_DATA_10_D3INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y123",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES_REG(62),
      O => OSERDES_TX_DATA_10_D3_INT
    );