ddr_6to1_16chan_rt_tx_timesim.vhd

FPGA之间的LVDS传输

      I => DATA_TO_OSERDES(93),
      O => DATA_TO_OSERDES_93_INBUF_B
    );
  DATA_TO_OSERDES_85_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y48",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(85),
      O => DATA_TO_OSERDES_85_INBUF_B
    );
  DATA_TO_OSERDES_77_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y94",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(77),
      O => DATA_TO_OSERDES_77_INBUF_B
    );
  DATA_TO_OSERDES_69_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y72",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(69),
      O => DATA_TO_OSERDES_69_INBUF_B
    );
  TX_CLOCK_PREBUF_OFF_D2_OUTFF : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y223",
      PATHPULSE => 396 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => TX_CLOCK_PREBUF_OFF_D2INV_OUTFF
    );
  TX_CLOCK_PREBUF_OFF_D1_OUTFF : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y223",
      PATHPULSE => 396 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => TX_CLOCK_PREBUF_OFF_D1INV_OUTFF
    );
  ODDR_TX_CLOCK : X_ODDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      SRTYPE => "ASYNC",
      LOC => "OLOGIC_X0Y223",
      INIT => '0'
    )
    port map (
      D1 => TX_CLOCK_PREBUF_OFF_D1INV_OUTFF,
      D2 => TX_CLOCK_PREBUF_OFF_D2INV_OUTFF,
      CE => GLOBAL_LOGIC1,
      C => TX_CLOCK_PREBUF_OFF_CLK1INV_2268,
      R => GND,
      S => GND,
      Q => TX_CLOCK_PREBUF
    );
  TX_CLOCK_PREBUF_OFF_CLK1INV : X_BUF
    generic map(
      LOC => "OLOGIC_X0Y223",
      PATHPULSE => 396 ps
    )
    port map (
      I => TXCLK_BUFGP,
      O => TX_CLOCK_PREBUF_OFF_CLK1INV_2268
    );
  DATA_TO_OSERDES_REG_88 : X_FF
    generic map(
      LOC => "SLICE_X0Y21",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_88_1_570,
      O => DATA_TO_OSERDES_REG(88),
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_88_1 : X_LUT6
    generic map(
      LOC => "SLICE_X0Y21",
      INIT => X"00F000F000F000F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR4 => VCC,
      ADR5 => VCC,
      ADR2 => DATA_TO_OSERDES_88_INBUF_B,
      ADR3 => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_88_1_570
    );
  DATA_TO_OSERDES_REG_85 : X_FF
    generic map(
      LOC => "SLICE_X0Y21",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_85_1_572,
      O => DATA_TO_OSERDES_REG(85),
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_85_1 : X_LUT6
    generic map(
      LOC => "SLICE_X0Y21",
      INIT => X"2222222222222222"
    )
    port map (
      ADR4 => VCC,
      ADR5 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      ADR0 => DATA_TO_OSERDES_85_INBUF_B,
      ADR1 => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_85_1_572
    );
  DATA_TO_OSERDES_REG_84 : X_FF
    generic map(
      LOC => "SLICE_X0Y21",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_84_1_569,
      O => DATA_TO_OSERDES_REG(84),
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_84_1 : X_LUT6
    generic map(
      LOC => "SLICE_X0Y21",
      INIT => X"3333000033330000"
    )
    port map (
      ADR0 => VCC,
      ADR5 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      ADR4 => DATA_TO_OSERDES_84_INBUF_B,
      ADR1 => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_84_1_569
    );
  DATA_TO_OSERDES_REG_87 : X_SFF
    generic map(
      LOC => "SLICE_X0Y22",
      INIT => '1'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_REG(87),
      SRST => GND,
      SSET => DATA_TO_OSERDES_87_INBUF_B,
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_REG_93 : X_SFF
    generic map(
      LOC => "SLICE_X0Y41",
      INIT => '1'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_REG(93),
      SRST => GND,
      SSET => DATA_TO_OSERDES_93_INBUF_B,
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_REG_71 : X_SFF
    generic map(
      LOC => "SLICE_X0Y42",
      INIT => '1'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_REG(71),
      SRST => GND,
      SSET => DATA_TO_OSERDES_71_INBUF_B,
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_REG_95 : X_SFF
    generic map(
      LOC => "SLICE_X0Y43",
      INIT => '1'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_REG(95),
      SRST => GND,
      SSET => DATA_TO_OSERDES_95_INBUF_B,
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_REG_56 : X_SFF
    generic map(
      LOC => "SLICE_X0Y44",
      INIT => '1'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_REG(56),
      SRST => GND,
      SSET => DATA_TO_OSERDES_56_INBUF_B,
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_REG_16 : X_FF
    generic map(
      LOC => "SLICE_X0Y45",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_16_1_601,
      O => DATA_TO_OSERDES_REG(16),
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_16_1 : X_LUT6
    generic map(
      LOC => "SLICE_X0Y45",
      INIT => X"00AA00AA00AA00AA"
    )
    port map (
      ADR4 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR5 => VCC,
      ADR0 => DATA_TO_OSERDES_16_INBUF_B,
      ADR3 => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_16_1_601
    );
  DATA_TO_OSERDES_REG_58 : X_FF
    generic map(
      LOC => "SLICE_X0Y46",
      INIT => '0'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_58_1_606,
      O => DATA_TO_OSERDES_REG(58),
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_58_1 : X_LUT6
    generic map(
      LOC => "SLICE_X0Y46",
      INIT => X"0000FF000000FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR5 => VCC,
      ADR3 => DATA_TO_OSERDES_58_INBUF_B,
      ADR4 => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_58_1_606
    );
  DATA_TO_OSERDES_REG_2 : X_SFF
    generic map(
      LOC => "SLICE_X0Y47",
      INIT => '1'
    )
    port map (
      CE => VCC,
      CLK => TXCLKDIV_BUFGP,
      I => DATA_TO_OSERDES_11_11,
      O => DATA_TO_OSERDES_REG(2),
      SRST => GND,
      SSET => DATA_TO_OSERDES_2_INBUF_B,
      SET => GND,
      RST => GND
    );
  DATA_TO_OSERDES_39_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y140",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(39),
      O => DATA_TO_OSERDES_39_INBUF_B
    );
  DATA_TO_OSERDES_80_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y142",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(80),
      O => DATA_TO_OSERDES_80_INBUF_B
    );
  DATA_TO_OSERDES_72_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y161",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(72),
      O => DATA_TO_OSERDES_72_INBUF_B
    );
  DATA_TO_OSERDES_64_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y162",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(64),
      O => DATA_TO_OSERDES_64_INBUF_B
    );
  DATA_TO_OSERDES_56_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y78",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(56),
      O => DATA_TO_OSERDES_56_INBUF_B
    );
  DATA_TO_OSERDES_48_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y157",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(48),
      O => DATA_TO_OSERDES_48_INBUF_B
    );
  OBUFDS_TX_DATA_10_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y123"
    )
    port map (
      I => TX_DATA_PREBUF(10),
      O => DATA_TX_P(10),
      OB => DATA_TX_N(10)
    );
  DATA_TO_OSERDES_81_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y143",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(81),
      O => DATA_TO_OSERDES_81_INBUF_B
    );
  DATA_TO_OSERDES_73_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y164",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(73),
      O => DATA_TO_OSERDES_73_INBUF_B
    );
  DATA_TO_OSERDES_65_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y144",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(65),
      O => DATA_TO_OSERDES_65_INBUF_B
    );
  DATA_TO_OSERDES_57_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y77",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(57),
      O => DATA_TO_OSERDES_57_INBUF_B
    );
  DATA_TO_OSERDES_49_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y165",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(49),
      O => DATA_TO_OSERDES_49_INBUF_B
    );
  OBUFDS_TX_DATA_11_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y97"
    )
    port map (
      I => TX_DATA_PREBUF(11),
      O => DATA_TX_P(11),
      OB => DATA_TX_N(11)
    );
  DATA_TO_OSERDES_90_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y192",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(90),
      O => DATA_TO_OSERDES_90_INBUF_B
    );
  DATA_TO_OSERDES_82_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y163",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(82),
      O => DATA_TO_OSERDES_82_INBUF_B
    );
  DATA_TO_OSERDES_74_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y86",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(74),
      O => DATA_TO_OSERDES_74_INBUF_B
    );
  DATA_TO_OSERDES_66_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y62",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(66),
      O => DATA_TO_OSERDES_66_INBUF_B
    );
  DATA_TO_OSERDES_58_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y64",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(58),
      O => DATA_TO_OSERDES_58_INBUF_B
    );
  RESET_IMUX : X_BUF
    generic map(
      LOC => "IOB_X0Y89",
      PATHPULSE => 396 ps
    )
    port map (
      I => RESET_INBUF_B,
      O => RESET_IBUF_1110
    );
  RESET_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y89",
      PATHPULSE => 396 ps
    )
    port map (
      I => RESET,
      O => RESET_INBUF_B
    );
  OBUFDS_TX_DATA_12_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y109"