ddr_6to1_16chan_rt_tx_timesim.vhd

FPGA之间的LVDS传输

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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.37
--  \   \         Application: netgen
--  /   /         Filename: DDR_6TO1_16CHAN_RT_TX_timesim.vhd
-- /___/   /\     Timestamp: Wed Aug 20 09:03:22 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 1 -pcf DDR_6TO1_16CHAN_RT_TX.pcf -rpw 100 -tpw 0 -ar Structure -tm DDR_6TO1_16CHAN_RT_TX -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim DDR_6TO1_16CHAN_RT_TX.ncd DDR_6TO1_16CHAN_RT_TX_timesim.vhd 
-- Device	: 5vsx50tff1136-1 (PRODUCTION 1.61 2008-05-28)
-- Input file	: DDR_6TO1_16CHAN_RT_TX.ncd
-- Output file	: E:\ISEworks\LVDS\xapp860\netgen\par\DDR_6TO1_16CHAN_RT_TX_timesim.vhd
-- # of Entities	: 1
-- Design Name	: DDR_6TO1_16CHAN_RT_TX
-- Xilinx	: K:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity DDR_6TO1_16CHAN_RT_TX is
  port (
    TXCLK : in STD_LOGIC := 'X'; 
    RESET : in STD_LOGIC := 'X'; 
    TXCLKDIV : in STD_LOGIC := 'X'; 
    CLOCK_TX_N : out STD_LOGIC; 
    CLOCK_TX_P : out STD_LOGIC; 
    TRAINING_DONE : in STD_LOGIC := 'X'; 
    DATA_TX_N : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    DATA_TX_P : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    DATA_TO_OSERDES : in STD_LOGIC_VECTOR ( 95 downto 0 ) 
  );
end DDR_6TO1_16CHAN_RT_TX;

architecture Structure of DDR_6TO1_16CHAN_RT_TX is
  signal TXCLKDIV_BUFGP : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal RESET_IBUF_1110 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal TXCLK_BUFGP : STD_LOGIC; 
  signal DATA_TO_OSERDES_11_11 : STD_LOGIC; 
  signal TX_CLOCK_PREBUF : STD_LOGIC; 
  signal DATA_TO_OSERDES_75_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_67_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_59_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_92_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_84_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_76_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_68_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_93_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_85_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_77_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_69_INBUF_B : STD_LOGIC; 
  signal TX_CLOCK_PREBUF_OFF_D2INV_OUTFF : STD_LOGIC; 
  signal TX_CLOCK_PREBUF_OFF_D1INV_OUTFF : STD_LOGIC; 
  signal TX_CLOCK_PREBUF_OFF_CLK1INV_2268 : STD_LOGIC; 
  signal DATA_TO_OSERDES_85_1_572 : STD_LOGIC; 
  signal DATA_TO_OSERDES_88_1_570 : STD_LOGIC; 
  signal DATA_TO_OSERDES_84_1_569 : STD_LOGIC; 
  signal DATA_TO_OSERDES_16_1_601 : STD_LOGIC; 
  signal DATA_TO_OSERDES_58_1_606 : STD_LOGIC; 
  signal DATA_TO_OSERDES_39_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_80_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_72_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_64_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_56_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_48_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_81_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_73_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_65_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_57_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_49_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_90_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_82_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_74_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_66_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_58_INBUF_B : STD_LOGIC; 
  signal RESET_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_91_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_83_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_43_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_35_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_27_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_19_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_60_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_52_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_44_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_36_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_28_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_61_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_53_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_45_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_37_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_29_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_70_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_62_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_54_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_46_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_38_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_71_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_63_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_55_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_47_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_13_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_30_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_22_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_14_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_31_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_23_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_15_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_40_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_32_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_24_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_16_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_41_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_33_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_25_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_17_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_50_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_42_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_34_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_26_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_18_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_51_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_9_INBUF_B : STD_LOGIC; 
  signal TRAINING_DONE_INBUF_B : STD_LOGIC; 
  signal TXCLKDIV_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_10_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_11_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_20_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_12_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_21_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_0_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_1_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_2_INBUF_B : STD_LOGIC; 
  signal TXCLK_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_3_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_4_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_5_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_6_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_7_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_8_INBUF_B : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_00_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_01_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_10_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_02_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_11_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_03_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_12_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_04_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_13_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_05_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_14_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_06_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_15_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_07_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_08_D1_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_SHIFTOUT2 : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_SHIFTOUT1 : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_TQ : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_CLKDIV_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_CLK_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_D6_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_D5_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_D4_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_D3_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_D2_INT : STD_LOGIC; 
  signal OSERDES_TX_DATA_09_D1_INT : STD_LOGIC; 
  signal DATA_TO_OSERDES_94_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_86_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_78_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_95_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_87_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_79_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_88_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_89_INBUF_B : STD_LOGIC; 
  signal DATA_TO_OSERDES_66_1_617 : STD_LOGIC; 
  signal DATA_TO_OSERDES_67_1_615 : STD_LOGIC; 
  signal DATA_TO_OSERDES_90_1_628 : STD_LOGIC; 
  signal DATA_TO_OSERDES_91_1_626 : STD_LOGIC; 
  signal DATA_TO_OSERDES_94_1_624 : STD_LOGIC; 
  signal DATA_TO_OSERDES_25_1_648 : STD_LOGIC; 
  signal DATA_TO_OSERDES_42_1_647 : STD_LOGIC; 
  signal DATA_TO_OSERDES_43_1_645 : STD_LOGIC; 
  signal DATA_TO_OSERDES_24_1_643 : STD_LOGIC; 
  signal DATA_TO_OSERDES_0_1_669 : STD_LOGIC; 
  signal DATA_TO_OSERDES_1_1_667 : STD_LOGIC; 
  signal DATA_TO_OSERDES_28_1_673 : STD_LOGIC; 
  signal DATA_TO_OSERDES_54_1_684 : STD_LOGIC; 
  signal DATA_TO_OSERDES_55_1_682 : STD_LOGIC; 
  signal DATA_TO_OSERDES_46_1_680 : STD_LOGIC; 
  signal DATA_TO_OSERDES_70_1_695 : STD_LOGIC; 
  signal DATA_TO_OSERDES_73_1_702 : STD_LOGIC; 
  signal DATA_TO_OSERDES_76_1_700 : STD_LOGIC; 
  signal DATA_TO_OSERDES_72_1_699 : STD_LOGIC; 
  signal DATA_TO_OSERDES_78_1_726 : STD_LOGIC; 
  signal DATA_TO_OSERDES_79_1_724 : STD_LOGIC; 
  signal DATA_TO_OSERDES_18_1_732 : STD_LOGIC; 
  signal DATA_TO_OSERDES_19_1_730 : STD_LOGIC; 
  signal DATA_TO_OSERDES_34_1_729 : STD_LOGIC; 
  signal DATA_TO_OSERDES_10_1_748 : STD_LOGIC; 
  signal DATA_TO_OSERDES_82_1_746 : STD_LOGIC; 
  signal DATA_TO_OSERDES_30_1_761 : STD_LOGIC; 
  signal DATA_TO_OSERDES_31_1_758 : STD_LOGIC; 
  signal DATA_TO_OSERDES_48_1_770 : STD_LOGIC; 
  signal DATA_TO_OSERDES_49_1_767 : STD_LOGIC; 
  signal DATA_TO_OSERDES_13_1_776 : STD_LOGIC; 
  signal DATA_TO_OSERDES_64_1_774 : STD_LOGIC; 
  signal DATA_TO_OSERDES_12_1_773 : STD_LOGIC; 
  signal DATA_TO_OSERDES_6_1_849 : STD_LOGIC; 
  signal DATA_TO_OSERDES_7_1_847 : STD_LOGIC; 
  signal DATA_TO_OSERDES_4_1_845 : STD_LOGIC; 
  signal DATA_TO_OSERDES_22_1_862 : STD_LOGIC; 
  signal DATA_TO_OSERDES_40_1_867 : STD_LOGIC; 
  signal DATA_TO_OSERDES_61_1_884 : STD_LOGIC; 
  signal DATA_TO_OSERDES_52_1_882 : STD_LOGIC; 
  signal DATA_TO_OSERDES_60_1_881 : STD_LOGIC; 
  signal DATA_TO_OSERDES_36_1_920 : STD_LOGIC; 
  signal DATA_TO_OSERDES_37_1_917 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal DATA_TO_OSERDES_REG : STD_LOGIC_VECTOR ( 95 downto 0 ); 
  signal TX_DATA_PREBUF : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  DATA_TO_OSERDES_75_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y132",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(75),
      O => DATA_TO_OSERDES_75_INBUF_B
    );
  DATA_TO_OSERDES_67_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y200",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(67),
      O => DATA_TO_OSERDES_67_INBUF_B
    );
  DATA_TO_OSERDES_59_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y81",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(59),
      O => DATA_TO_OSERDES_59_INBUF_B
    );
  OBUFDS_TX_DATA_13_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y125"
    )
    port map (
      I => TX_DATA_PREBUF(13),
      O => DATA_TX_P(13),
      OB => DATA_TX_N(13)
    );
  DATA_TO_OSERDES_92_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y75",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(92),
      O => DATA_TO_OSERDES_92_INBUF_B
    );
  DATA_TO_OSERDES_84_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y176",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(84),
      O => DATA_TO_OSERDES_84_INBUF_B
    );
  DATA_TO_OSERDES_76_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y135",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(76),
      O => DATA_TO_OSERDES_76_INBUF_B
    );
  DATA_TO_OSERDES_68_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y73",
      PATHPULSE => 396 ps
    )
    port map (
      I => DATA_TO_OSERDES(68),
      O => DATA_TO_OSERDES_68_INBUF_B
    );
  OBUFDS_TX_DATA_14_OBUFDS : X_OBUFDS
    generic map(
      LOC => "IOB_X0Y43"
    )
    port map (
      I => TX_DATA_PREBUF(14),
      O => DATA_TX_P(14),
      OB => DATA_TX_N(14)
    );
  DATA_TO_OSERDES_93_IBUF : X_BUF
    generic map(
      LOC => "IOB_X0Y70",
      PATHPULSE => 396 ps
    )
    port map (