复件 ddr_6to1_16chan_rt_rx_timesim.sdf

FPGA之间的LVDS传输

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  (DESIGN "DDR_6TO1_16CHAN_RT_RX")
  (DATE "Wed Aug 20 08:44:17 2008")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx SDF Writer")
  (VERSION "K.37")
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  (VOLTAGE 0.95)
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