ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal ISERDES_RX_MON_15_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_15_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_15_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_15_O : STD_LOGIC; 
  signal ISERDES_RX_MON_15_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_15_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_15_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_15_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_15_D : STD_LOGIC; 
  signal ISERDES_RX_MON_07_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_07_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_07_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_07_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_07_O : STD_LOGIC; 
  signal ISERDES_RX_MON_07_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_07_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_07_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_07_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_07_D : STD_LOGIC; 
  signal ISERDES_RX_MON_16_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_16_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_16_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_16_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_16_O : STD_LOGIC; 
  signal ISERDES_RX_MON_16_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_16_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_16_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_16_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_16_D : STD_LOGIC; 
  signal ISERDES_RX_MON_08_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_08_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_08_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_08_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_08_O : STD_LOGIC; 
  signal ISERDES_RX_MON_08_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_08_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_08_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_08_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_08_D : STD_LOGIC; 
  signal ISERDES_RX_MON_09_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_09_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_09_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_09_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_09_O : STD_LOGIC; 
  signal ISERDES_RX_MON_09_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_09_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_09_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_09_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_09_D : STD_LOGIC; 
  signal ISERDES_RX_CNTL_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_CNTL_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_CNTL_Q2 : STD_LOGIC; 
  signal ISERDES_RX_CNTL_Q1 : STD_LOGIC; 
  signal ISERDES_RX_CNTL_O : STD_LOGIC; 
  signal ISERDES_RX_CNTL_OFB : STD_LOGIC; 
  signal ISERDES_RX_CNTL_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_CNTL_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_CNTL_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_CNTL_D : STD_LOGIC; 
  signal IODELAY_RX_DATA_00_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_00_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_01_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_01_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_10_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_10_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_02_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_02_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_11_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_11_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_03_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_03_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_12_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_12_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_04_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_04_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_13_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_13_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_05_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_05_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_14_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_14_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_06_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_06_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_15_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_15_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_07_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_07_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_08_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_08_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_DATA_09_C_INT : STD_LOGIC; 
  signal IODELAY_RX_DATA_09_ODATAIN : STD_LOGIC; 
  signal ISERDES_CLOCK_RX_ODATAIN : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_166 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_DATA_ALIGNED_RTx : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_166 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_166 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In2166 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In21661_2024 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd1_In : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_3_166 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_166 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_166 : STD_LOGIC; 
  signal N299 : STD_LOGIC; 
  signal N300 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd2_In : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd3_In_2428 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_166 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_166 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_166 : STD_LOGIC; 
  signal N298 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In : STD_LOGIC; 
  signal N297 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd3_In_2983 : STD_LOGIC; 
  signal N301 : STD_LOGIC; 
  signal N302 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd1_In : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd2_In : STD_LOGIC; 
  signal Mshreg_INC_CAPTURE_2_3187 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_1_166 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_2_166 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_0_166 : STD_LOGIC; 
  signal wr_en_and0000 : STD_LOGIC; 
  signal Mshreg_DEC_CAPTURE_2_4125 : STD_LOGIC; 
  signal N304 : STD_LOGIC; 
  signal N303 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd1_In : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_DATA_ALIGNEDx : STD_LOGIC; 
  signal Mshreg_RESET_SM_15_4879 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd3_In_5059 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In : STD_LOGIC; 
  signal Mshreg_BITSLIP_CAPTURE_2_5841 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count12 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count15 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count9 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count6 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_Mcount_count3 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0002 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0001 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0004 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin_xor0003 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0004 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0003 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0002 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_xor0001 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0004 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0003 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0002 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_xor0001 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0002 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0001 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0004 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin_xor0003 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_almost_empty_i_or0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count6 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count9 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count3 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count12 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_Mcount_count15 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NLW_ISERDES_CLOCK_RX_C_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_INC_CAPTURE_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_DEC_CAPTURE_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_RESET_SM_15_Q15_UNCONNECTED : STD_LOGIC; 
  signal NLW_Mshreg_BITSLIP_CAPTURE_2_Q15_UNCONNECTED : STD_LOGIC; 
  signal CHAN_SEL : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal ICE_TO_ISERDES : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal ICE_TO_ISERDES_RT : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal TAP_COUNTER_03_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_11_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal INC_TO_ISERDES : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal INC_TO_ISERDES_RT : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal DATA_FROM_ISERDES_TEMP : STD_LOGIC_VECTOR ( 67 downto 0 ); 
  signal TAP_COUNTER_08_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_16_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg_d1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_bin : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal CHAN_SEL_RT : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal ICE_TO_MONITOR_RT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal INC_TO_MONITOR_RT : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_counter0_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BITSLIP_TO_ISERDES : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_1_delay_counter_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_0_delay_counter_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal TAP_COUNTER_04_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_12_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_count_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_00_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_09_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_counter1_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_0_channel_counter_counter_value_preserver : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_1_channel_counter_counter_value_preserver : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal TAP_COUNTER_05_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_13_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RESET_SM : STD_LOGIC_VECTOR ( 15 downto 15 ); 
  signal TAP_COUNTER_01_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal DATA_TO_MACHINE : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_count_d3 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal RESOURCE_SHARING_CONTROL_0_channel_counter_Madd_temp_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal DATA_FROM_ISERDES_MON : STD_LOGIC_VECTOR ( 67 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter_total_counter_value_int : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg_d1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_gc_asreg : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal MONITOR_TO_RT : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_RXDATA_PREV : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal din : STD_LOGIC_VECTOR ( 63 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_STORE_STATUS : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal RT_WINDOW_MONITOR_0_SAMPLE_WINDOW : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_wr_pntr_bin : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_02_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_06_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_07_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_10_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_14_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal TAP_COUNTER_15_counter_value_int : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal DATA_TO_RT : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal U_FIFO_BU2_U0_grf_rf_gcx_clkx_rd_pntr_gc_asreg : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_CVS : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_addsub0000 : STD_LOGIC_VECTOR ( 5 downto 4 ); 
  signal RESOURCE_SHARING_CONTROL_1_channel_counter_Madd_temp_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
  signal DATA_RX_IDLY : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal DATA_RX_IDLY_MON : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal TAP_COUNTER_15_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_11_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_02_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal TAP_COUNTER_16_Maddsub_counter_value_int_addsub0000_cy : STD_LOGIC_VECTOR ( 3 downto 3 ); 
  signal BIT_ALIGN_MACHINE_0_machine_counter