ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal IODELAY_RX_CNTL_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_00_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_00_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_01_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_01_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_10_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_10_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_02_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_02_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_11_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_11_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_03_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_03_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_12_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_12_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_04_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_04_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_13_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_13_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_05_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_05_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_14_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_14_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_06_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_06_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_15_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_15_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_07_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_07_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_08_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_08_ODATAIN : STD_LOGIC; 
  signal IODELAY_RX_MON_09_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_09_ODATAIN : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY0 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY1 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY2 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY3 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY4 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY5 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY6 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_ECCPARITY7 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP0 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP1 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP2 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP3 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP4 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP5 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP6 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DOP7 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_DBITERR : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SBITERR : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU0 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU1 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU2 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU3 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU4 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRU5 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL0 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL1 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL2 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL3 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL4 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRADDRL5 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU0 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU1 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU2 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU3 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU4 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRU5 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL0 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL1 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL2 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL3 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL4 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDADDRL5 : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDRCLKL_INT : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_WRCLKL_INT : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDCLKL_INT : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_SSRL_INT : STD_LOGIC;
 
  signal U_FIFO_BU2_U0_grf_rf_mem_gbm_gbmg_gbmga_ngecc_bmg_blk_mem_generator_valid_cstr_ramloop_0_ram_r_v5_noinit_ram_SDP_WIDE_PRIM36_noeccerr_SDP_RDENL_INT : STD_LOGIC;
 
  signal IODELAY_RX_MON_CNTL_C_INT : STD_LOGIC; 
  signal IODELAY_RX_MON_CNTL_ODATAIN : STD_LOGIC; 
  signal ISERDES_RX_MON_00_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_00_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_00_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_00_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_00_O : STD_LOGIC; 
  signal ISERDES_RX_MON_00_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_00_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_00_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_00_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_00_D : STD_LOGIC; 
  signal ISERDES_RX_MON_01_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_01_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_01_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_01_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_01_O : STD_LOGIC; 
  signal ISERDES_RX_MON_01_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_01_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_01_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_01_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_01_D : STD_LOGIC; 
  signal ISERDES_RX_MON_10_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_10_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_10_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_10_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_10_O : STD_LOGIC; 
  signal ISERDES_RX_MON_10_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_10_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_10_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_10_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_10_D : STD_LOGIC; 
  signal ISERDES_RX_MON_02_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_02_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_02_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_02_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_02_O : STD_LOGIC; 
  signal ISERDES_RX_MON_02_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_02_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_02_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_02_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_02_D : STD_LOGIC; 
  signal ISERDES_RX_MON_11_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_11_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_11_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_11_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_11_O : STD_LOGIC; 
  signal ISERDES_RX_MON_11_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_11_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_11_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_11_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_11_D : STD_LOGIC; 
  signal ISERDES_RX_MON_03_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_03_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_03_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_03_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_03_O : STD_LOGIC; 
  signal ISERDES_RX_MON_03_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_03_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_03_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_03_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_03_D : STD_LOGIC; 
  signal ISERDES_RX_MON_12_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_12_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_12_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_12_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_12_O : STD_LOGIC; 
  signal ISERDES_RX_MON_12_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_12_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_12_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_12_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_12_D : STD_LOGIC; 
  signal ISERDES_RX_MON_04_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_04_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_04_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_04_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_04_O : STD_LOGIC; 
  signal ISERDES_RX_MON_04_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_04_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_04_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_04_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_04_D : STD_LOGIC; 
  signal ISERDES_RX_MON_13_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_13_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_13_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_13_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_13_O : STD_LOGIC; 
  signal ISERDES_RX_MON_13_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_13_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_13_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_13_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_13_D : STD_LOGIC; 
  signal ISERDES_RX_MON_05_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_05_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_05_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_05_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_05_O : STD_LOGIC; 
  signal ISERDES_RX_MON_05_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_05_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_05_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_05_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_05_D : STD_LOGIC; 
  signal ISERDES_RX_MON_14_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_14_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_14_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_14_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_14_O : STD_LOGIC; 
  signal ISERDES_RX_MON_14_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_14_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_14_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_14_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_14_D : STD_LOGIC; 
  signal ISERDES_RX_MON_06_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_MON_06_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_MON_06_Q2 : STD_LOGIC; 
  signal ISERDES_RX_MON_06_Q1 : STD_LOGIC; 
  signal ISERDES_RX_MON_06_O : STD_LOGIC; 
  signal ISERDES_RX_MON_06_OFB : STD_LOGIC; 
  signal ISERDES_RX_MON_06_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_06_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_MON_06_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_MON_06_D : STD_LOGIC; 
  signal ISERDES_RX_MON_15_SHIFTOUT2 : STD_LOGIC;