ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal DATA_TO_MACHINE_mux0000_3_123_8088 : STD_LOGIC; 
  signal N75 : STD_LOGIC; 
  signal N59 : STD_LOGIC; 
  signal N69 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_87_8092 : STD_LOGIC; 
  signal N93 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_87_8094 : STD_LOGIC; 
  signal N81 : STD_LOGIC; 
  signal N231 : STD_LOGIC; 
  signal N240 : STD_LOGIC; 
  signal N67 : STD_LOGIC; 
  signal N79 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_87_8100 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_139_8101 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_87_8102 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_87_8103 : STD_LOGIC; 
  signal N1031 : STD_LOGIC; 
  signal N218 : STD_LOGIC; 
  signal N255 : STD_LOGIC; 
  signal N274 : STD_LOGIC; 
  signal START_ALIGN_RT : STD_LOGIC; 
  signal N235 : STD_LOGIC; 
  signal N234 : STD_LOGIC; 
  signal N245 : STD_LOGIC; 
  signal N77 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_1_123_8114 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_2_123_8115 : STD_LOGIC; 
  signal N237 : STD_LOGIC; 
  signal N1011 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_0_123_8118 : STD_LOGIC; 
  signal N243 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In147_8125 : STD_LOGIC; 
  signal N295 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal N253 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In289_8131 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In244_8132 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_lt00021 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In16_8134 : STD_LOGIC; 
  signal N28 : STD_LOGIC; 
  signal N277 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_18 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_19 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_gwas_wsts_comp2 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or000036_8153 : STD_LOGIC; 
  signal RXCLK_USR_INBUF_B : STD_LOGIC; 
  signal CLK200_INBUF_B : STD_LOGIC; 
  signal DATA_RX_P_16_INBUF_DS : STD_LOGIC; 
  signal INC_PAD_INBUF_B : STD_LOGIC; 
  signal RT_MANUAL_DISABLE_INBUF_B : STD_LOGIC; 
  signal BITSLIP_PAD_INBUF_B : STD_LOGIC; 
  signal DATA_RX_N_0_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_1_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_2_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_3_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_4_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_5_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_6_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_7_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_0_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_8_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_1_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_9_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_2_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_3_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_10_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_11_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_12_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_13_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_14_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_15_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_N_16_INBUF_DS : STD_LOGIC; 
  signal RESET_INBUF_B : STD_LOGIC; 
  signal DATA_RX_P_10_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_11_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_12_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_13_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_14_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_15_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_4_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_5_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_6_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_7_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_8_INBUF_DS : STD_LOGIC; 
  signal DATA_RX_P_9_INBUF_DS : STD_LOGIC; 
  signal CLOCK_RX_P_INBUF_DS : STD_LOGIC; 
  signal IDELAYCTRL_RESET_INBUF_B : STD_LOGIC; 
  signal DEC_PAD_INBUF_B : STD_LOGIC; 
  signal IDLY_RESET_INBUF_B : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_00_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_01_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_10_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_02_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_11_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_03_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_12_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_04_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_13_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_05_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_14_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_06_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_15_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_07_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_08_D : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_SHIFTOUT2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_SHIFTOUT1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_Q2 : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_Q1 : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_O : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_OFB : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_CLKDIV_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_CLKB_INTNOT : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_CLK_INT : STD_LOGIC; 
  signal ISERDES_RX_DATA_09_D : STD_LOGIC; 
  signal IODELAY_RX_CNTL_C_INT : STD_LOGIC;