ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

  signal RX_DATA_CE_07 : STD_LOGIC; 
  signal RX_DATA_CE_10 : STD_LOGIC; 
  signal RX_DATA_CE_14 : STD_LOGIC; 
  signal RX_DATA_CE_15 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_machine_counter_N23 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_machine_counter_N21 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_3_77_7528 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_49_7534 : STD_LOGIC; 
  signal RX_MON_CE_00 : STD_LOGIC; 
  signal RX_MON_CE_01 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In2193_7642 : STD_LOGIC; 
  signal RX_MON_CE_02 : STD_LOGIC; 
  signal RX_MON_CE_10 : STD_LOGIC; 
  signal RX_MON_CE_03 : STD_LOGIC; 
  signal RX_MON_CE_11 : STD_LOGIC; 
  signal RX_MON_CE_04 : STD_LOGIC; 
  signal RX_MON_CE_12 : STD_LOGIC; 
  signal RX_MON_CE_05 : STD_LOGIC; 
  signal RX_MON_CE_13 : STD_LOGIC; 
  signal RX_MON_CE_06 : STD_LOGIC; 
  signal RX_MON_CE_14 : STD_LOGIC; 
  signal RX_MON_CE_07 : STD_LOGIC; 
  signal RX_MON_CE_15 : STD_LOGIC; 
  signal RX_MON_CE_08 : STD_LOGIC; 
  signal RX_MON_CE_09 : STD_LOGIC; 
  signal N109 : STD_LOGIC; 
  signal N263 : STD_LOGIC; 
  signal N611 : STD_LOGIC; 
  signal rd_en_7665 : STD_LOGIC; 
  signal almost_empty : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_almost_empty_i_or000035_7668 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_RAM_EMPTY_FB_inv : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_7670 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_22_7673 : STD_LOGIC; 
  signal N57 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_cmp_lt0000 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_c1_dout_i85_7681 : STD_LOGIC; 
  signal N273 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In2330_7685 : STD_LOGIC; 
  signal N275 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd14 : STD_LOGIC; 
  signal BITSLIP_00 : STD_LOGIC; 
  signal BITSLIP_PULSE_7694 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_49_7697 : STD_LOGIC; 
  signal BITSLIP_01 : STD_LOGIC; 
  signal BITSLIP_02 : STD_LOGIC; 
  signal BITSLIP_10 : STD_LOGIC; 
  signal BITSLIP_03 : STD_LOGIC; 
  signal BITSLIP_11 : STD_LOGIC; 
  signal BITSLIP_04 : STD_LOGIC; 
  signal BITSLIP_12 : STD_LOGIC; 
  signal BITSLIP_05 : STD_LOGIC; 
  signal BITSLIP_13 : STD_LOGIC; 
  signal BITSLIP_06 : STD_LOGIC; 
  signal BITSLIP_14 : STD_LOGIC; 
  signal BITSLIP_07 : STD_LOGIC; 
  signal BITSLIP_15 : STD_LOGIC; 
  signal BITSLIP_08 : STD_LOGIC; 
  signal BITSLIP_09 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or000036_7715 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_i_or0000100_7716 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_gwas_wsts_c2_dout_i85_7718 : STD_LOGIC; 
  signal U_FIFO_BU2_N49 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_22_7738 : STD_LOGIC; 
  signal N268 : STD_LOGIC; 
  signal N269 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_138_7747 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_139_7748 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_133_7749 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_49_7750 : STD_LOGIC; 
  signal N73 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_0_22_7752 : STD_LOGIC; 
  signal TRAINING_DONE_OBUF_7754 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_138_7755 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_139_7756 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_133_7757 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_49_7758 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_1_22_7759 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_138_7760 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_139_7761 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_133_7762 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_22_7764 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_138_7765 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_133_7766 : STD_LOGIC; 
  signal N113 : STD_LOGIC; 
  signal N259 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_0_77_7774 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_0_42_7775 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_0_22_7776 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_1_77_7777 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_1_42_7778 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_1_22_7779 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_2_42_7780 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_2_22_7781 : STD_LOGIC; 
  signal N107 : STD_LOGIC; 
  signal N265 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_133_7784 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_138_7788 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_139_7791 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_3_22_7793 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N13 : STD_LOGIC; 
  signal MON_BITSLIP_16 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_133_7797 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_139_7802 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_133_7805 : STD_LOGIC; 
  signal BITSLIP_CAPTURE_3_Q : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_138_7810 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_139_7813 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In36_7815 : STD_LOGIC; 
  signal START_ALIGN : STD_LOGIC; 
  signal N49 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_138_7820 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_139_7823 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_rd_rst_comb : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_rd_rst_asreg_d2_7826 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_rd_rst_asreg_7827 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In96_7828 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In95_7829 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N26 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_In31_7831 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_49_7834 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_almost_empty_i_or0000112_7837 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_rd_rst_asreg_d1_7839 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_STORE : STD_LOGIC; 
  signal N241 : STD_LOGIC; 
  signal N293 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_16 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_1 : STD_LOGIC; 
  signal RX_IDELAYCTRL_MapLib_sig_17 : STD_LOGIC; 
  signal IDELAY_READY_OBUF_7848 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_comp1 : STD_LOGIC; 
  signal U_FIFO_BU2_N51 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_COUNT_SAMPLE : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In106_7854 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In143_7860 : STD_LOGIC; 
  signal N267 : STD_LOGIC; 
  signal DEC_CAPTURE_3_Q : STD_LOGIC; 
  signal DATA_RX_FIFO_VLD_OBUF_7865 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In120_7870 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In250_7874 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In228_7875 : STD_LOGIC; 
  signal N238 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_mem_tmp_ram_rd_en : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N17 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_wr_rst_asreg_d2_7880 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_cmp_lt0000 : STD_LOGIC; 
  signal N278 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_rd_gras_rsts_ram_empty_fb_i_or0000100_7883 : STD_LOGIC; 
  signal N281 : STD_LOGIC; 
  signal DATA_RX_FIFO_0_OBUF_7886 : STD_LOGIC; 
  signal DATA_RX_FIFO_1_OBUF_7887 : STD_LOGIC; 
  signal DATA_RX_FIFO_2_OBUF_7888 : STD_LOGIC; 
  signal DATA_RX_FIFO_3_OBUF_7889 : STD_LOGIC; 
  signal DATA_RX_FIFO_4_OBUF_7890 : STD_LOGIC; 
  signal DATA_RX_FIFO_5_OBUF_7891 : STD_LOGIC; 
  signal DATA_RX_FIFO_6_OBUF_7892 : STD_LOGIC; 
  signal DATA_RX_FIFO_7_OBUF_7893 : STD_LOGIC; 
  signal DATA_RX_FIFO_8_OBUF_7894 : STD_LOGIC; 
  signal DATA_RX_FIFO_9_OBUF_7895 : STD_LOGIC; 
  signal DATA_RX_FIFO_10_OBUF_7898 : STD_LOGIC; 
  signal DATA_RX_FIFO_11_OBUF_7899 : STD_LOGIC; 
  signal DATA_RX_FIFO_20_OBUF_7900 : STD_LOGIC; 
  signal DATA_RX_FIFO_12_OBUF_7901 : STD_LOGIC; 
  signal DATA_RX_FIFO_21_OBUF_7902 : STD_LOGIC; 
  signal DATA_RX_FIFO_13_OBUF_7903 : STD_LOGIC; 
  signal DATA_RX_FIFO_30_OBUF_7904 : STD_LOGIC; 
  signal DATA_RX_FIFO_22_OBUF_7905 : STD_LOGIC; 
  signal DATA_RX_FIFO_14_OBUF_7906 : STD_LOGIC; 
  signal DATA_RX_FIFO_31_OBUF_7907 : STD_LOGIC; 
  signal DATA_RX_FIFO_23_OBUF_7908 : STD_LOGIC; 
  signal DATA_RX_FIFO_15_OBUF_7909 : STD_LOGIC; 
  signal DATA_RX_FIFO_40_OBUF_7910 : STD_LOGIC; 
  signal DATA_RX_FIFO_32_OBUF_7911 : STD_LOGIC; 
  signal DATA_RX_FIFO_24_OBUF_7912 : STD_LOGIC; 
  signal DATA_RX_FIFO_16_OBUF_7913 : STD_LOGIC; 
  signal DATA_RX_FIFO_41_OBUF_7914 : STD_LOGIC; 
  signal DATA_RX_FIFO_33_OBUF_7915 : STD_LOGIC; 
  signal DATA_RX_FIFO_25_OBUF_7916 : STD_LOGIC; 
  signal DATA_RX_FIFO_17_OBUF_7917 : STD_LOGIC; 
  signal DATA_RX_FIFO_50_OBUF_7918 : STD_LOGIC; 
  signal DATA_RX_FIFO_42_OBUF_7919 : STD_LOGIC; 
  signal DATA_RX_FIFO_34_OBUF_7920 : STD_LOGIC; 
  signal DATA_RX_FIFO_26_OBUF_7921 : STD_LOGIC; 
  signal DATA_RX_FIFO_18_OBUF_7922 : STD_LOGIC; 
  signal DATA_RX_FIFO_51_OBUF_7923 : STD_LOGIC; 
  signal DATA_RX_FIFO_43_OBUF_7924 : STD_LOGIC; 
  signal DATA_RX_FIFO_35_OBUF_7925 : STD_LOGIC; 
  signal DATA_RX_FIFO_27_OBUF_7926 : STD_LOGIC; 
  signal DATA_RX_FIFO_19_OBUF_7927 : STD_LOGIC; 
  signal DATA_RX_FIFO_60_OBUF_7928 : STD_LOGIC; 
  signal DATA_RX_FIFO_52_OBUF_7929 : STD_LOGIC; 
  signal DATA_RX_FIFO_44_OBUF_7930 : STD_LOGIC; 
  signal DATA_RX_FIFO_36_OBUF_7931 : STD_LOGIC; 
  signal DATA_RX_FIFO_28_OBUF_7932 : STD_LOGIC; 
  signal DATA_RX_FIFO_61_OBUF_7933 : STD_LOGIC; 
  signal DATA_RX_FIFO_53_OBUF_7934 : STD_LOGIC; 
  signal DATA_RX_FIFO_45_OBUF_7935 : STD_LOGIC; 
  signal DATA_RX_FIFO_37_OBUF_7936 : STD_LOGIC; 
  signal DATA_RX_FIFO_29_OBUF_7937 : STD_LOGIC; 
  signal DATA_RX_FIFO_62_OBUF_7938 : STD_LOGIC; 
  signal DATA_RX_FIFO_54_OBUF_7939 : STD_LOGIC; 
  signal DATA_RX_FIFO_46_OBUF_7940 : STD_LOGIC; 
  signal DATA_RX_FIFO_38_OBUF_7941 : STD_LOGIC; 
  signal DATA_RX_FIFO_63_OBUF_7942 : STD_LOGIC; 
  signal DATA_RX_FIFO_55_OBUF_7943 : STD_LOGIC; 
  signal DATA_RX_FIFO_47_OBUF_7944 : STD_LOGIC; 
  signal DATA_RX_FIFO_39_OBUF_7945 : STD_LOGIC; 
  signal DATA_RX_FIFO_56_OBUF_7946 : STD_LOGIC; 
  signal DATA_RX_FIFO_48_OBUF_7947 : STD_LOGIC; 
  signal DATA_RX_FIFO_57_OBUF_7948 : STD_LOGIC; 
  signal DATA_RX_FIFO_49_OBUF_7949 : STD_LOGIC; 
  signal DATA_RX_FIFO_58_OBUF_7950 : STD_LOGIC; 
  signal DATA_RX_FIFO_59_OBUF_7951 : STD_LOGIC; 
  signal RXCLK_TEMP : STD_LOGIC; 
  signal CLK200_BUFGP : STD_LOGIC; 
  signal CLOCK_RX_ISERDES_OUT : STD_LOGIC; 
  signal N53 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_138_8061 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_87_8062 : STD_LOGIC; 
  signal N63 : STD_LOGIC; 
  signal N89 : STD_LOGIC; 
  signal N83 : STD_LOGIC; 
  signal N43 : STD_LOGIC; 
  signal N971 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In148_8068 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In182_8069 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_49_8072 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_2_87_8073 : STD_LOGIC; 
  signal N47 : STD_LOGIC; 
  signal N55 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_87_8076 : STD_LOGIC; 
  signal N85 : STD_LOGIC; 
  signal N87 : STD_LOGIC; 
  signal N991 : STD_LOGIC; 
  signal N71 : STD_LOGIC; 
  signal N1051 : STD_LOGIC; 
  signal N95 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In279_8084 : STD_LOGIC; 
  signal N292 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In1241_8086 : STD_LOGIC; 
  signal N271 : STD_LOGIC;