ddr_6to1_16chan_rt_rx_timesim.vhd

FPGA之间的LVDS传输

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.37
--  \   \         Application: netgen
--  /   /         Filename: DDR_6TO1_16CHAN_RT_RX_timesim.vhd
-- /___/   /\     Timestamp: Sun Aug 24 13:08:56 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 1 -pcf DDR_6TO1_16CHAN_RT_RX.pcf -rpw 100 -tpw 0 -ar Structure -tm DDR_6TO1_16CHAN_RT_RX -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim DDR_6TO1_16CHAN_RT_RX.ncd DDR_6TO1_16CHAN_RT_RX_timesim.vhd 
-- Device	: 5vsx50tff1136-1 (PRODUCTION 1.61 2008-05-28)
-- Input file	: DDR_6TO1_16CHAN_RT_RX.ncd
-- Output file	: E:\ISEworks\LVDS\LVDS_4to1\netgen\par\DDR_6TO1_16CHAN_RT_RX_timesim.vhd
-- # of Entities	: 1
-- Design Name	: DDR_6TO1_16CHAN_RT_RX
-- Xilinx	: K:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity DDR_6TO1_16CHAN_RT_RX is
  port (
    RXCLKDIV : out STD_LOGIC; 
    RESET : in STD_LOGIC := 'X'; 
    RT_MANUAL_DISABLE : in STD_LOGIC := 'X'; 
    IDLY_RESET : in STD_LOGIC := 'X'; 
    DEC_PAD : in STD_LOGIC := 'X'; 
    CLOCK_RX_N : in STD_LOGIC := 'X'; 
    CLOCK_RX_P : in STD_LOGIC := 'X'; 
    IDELAY_READY : out STD_LOGIC; 
    CLK200 : in STD_LOGIC := 'X'; 
    BITSLIP_PAD : in STD_LOGIC := 'X'; 
    RXCLK_USR : in STD_LOGIC := 'X'; 
    RXCLK : out STD_LOGIC; 
    DATA_RX_FIFO_VLD : out STD_LOGIC; 
    IDELAYCTRL_RESET : in STD_LOGIC := 'X'; 
    INC_PAD : in STD_LOGIC := 'X'; 
    TRAINING_DONE : out STD_LOGIC; 
    TAP_00 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_01 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_02 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_03 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_04 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_05 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_10 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_06 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_11 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_07 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_12 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_08 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_13 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_09 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_14 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_15 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_16 : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    TAP_CLK : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    DATA_RX_FIFO : out STD_LOGIC_VECTOR ( 63 downto 0 ); 
    DATA_RX_N : in STD_LOGIC_VECTOR ( 16 downto 0 ); 
    DATA_RX_P : in STD_LOGIC_VECTOR ( 16 downto 0 ) 
  );
end DDR_6TO1_16CHAN_RT_RX;

architecture Structure of DDR_6TO1_16CHAN_RT_RX is
  signal RXCLKDIV_OBUF_6952 : STD_LOGIC; 
  signal ICE_FROM_MACHINE : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal N01 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal INC_CAPTURE_0_Q : STD_LOGIC; 
  signal INC_CAPTURE_2_Q : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal INC_PULSE_6974 : STD_LOGIC; 
  signal DEC_PULSE_6976 : STD_LOGIC; 
  signal RX_DATA_RESET : STD_LOGIC; 
  signal RX_DATA_CE_03 : STD_LOGIC; 
  signal RX_DATA_CE_11 : STD_LOGIC; 
  signal RX_DATA_INC_03 : STD_LOGIC; 
  signal RX_DATA_INC_11 : STD_LOGIC; 
  signal wr_en_7001 : STD_LOGIC; 
  signal RX_DATA_CE_08 : STD_LOGIC; 
  signal RX_DATA_CE_16 : STD_LOGIC; 
  signal RX_DATA_INC_08 : STD_LOGIC; 
  signal RX_DATA_INC_16 : STD_LOGIC; 
  signal N103 : STD_LOGIC; 
  signal ICE_MONITOR : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N102 : STD_LOGIC; 
  signal N106 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal N104 : STD_LOGIC; 
  signal ICE_DATABUS : STD_LOGIC; 
  signal INC_MONITOR : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_7058 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_7059 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_7060 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd1_7062 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_7063 : STD_LOGIC; 
  signal RESET_IBUF_7064 : STD_LOGIC; 
  signal BITSLIP_FROM_MACHINE : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_COUNT0 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd3_7085 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd1_7087 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd2_7088 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd1_7089 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd3_7091 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_CS_FSM_FFd2_7092 : STD_LOGIC; 
  signal N41 : STD_LOGIC; 
  signal N61 : STD_LOGIC; 
  signal RX_DATA_CE_04 : STD_LOGIC; 
  signal RX_DATA_CE_12 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_UD_DELAY : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_UD_DELAY : STD_LOGIC; 
  signal RX_DATA_INC_04 : STD_LOGIC; 
  signal RX_DATA_INC_12 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal INC_DATABUS : STD_LOGIC; 
  signal RXCLK_USR_BUFGP : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_ram_rd_en : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_ram_wr_en : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd1_7170 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd2_7171 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_7172 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_7173 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd3_7174 : STD_LOGIC; 
  signal DATA_ALIGNED : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_RESET : STD_LOGIC; 
  signal RX_DATA_CE_00 : STD_LOGIC; 
  signal RX_DATA_INC_00 : STD_LOGIC; 
  signal RX_DATA_CE_09 : STD_LOGIC; 
  signal RX_DATA_INC_09 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_UD : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_COUNT : STD_LOGIC; 
  signal DEC_CAPTURE_0_Q : STD_LOGIC; 
  signal DEC_CAPTURE_2_Q : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_COUNT1 : STD_LOGIC; 
  signal N02 : STD_LOGIC; 
  signal N208 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_0_COUNT_CHAN : STD_LOGIC; 
  signal N247 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd1_1_7270 : STD_LOGIC; 
  signal RX_DATA_CE_05 : STD_LOGIC; 
  signal RX_DATA_CE_13 : STD_LOGIC; 
  signal RX_DATA_INC_05 : STD_LOGIC; 
  signal RX_DATA_INC_13 : STD_LOGIC; 
  signal DATA_ALIGNED_RT : STD_LOGIC; 
  signal RX_DATA_CE_01 : STD_LOGIC; 
  signal RX_DATA_INC_01 : STD_LOGIC; 
  signal BITSLIP_CAPTURE_0_Q : STD_LOGIC; 
  signal BITSLIP_CAPTURE_2_Q : STD_LOGIC; 
  signal INC_FROM_MACHINE : STD_LOGIC; 
  signal N144 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_channel_counter_temp_4_1_7305 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_22_7306 : STD_LOGIC; 
  signal INC_TO_ISERDES_RT_cmp_eq000111_7309 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_gl0_wr_gwas_wsts_ram_full_fb_i_7310 : STD_LOGIC; 
  signal N111 : STD_LOGIC; 
  signal N136 : STD_LOGIC; 
  signal N261 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_wr_rst_asreg_d1_7318 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_wr_rst_asreg_7319 : STD_LOGIC; 
  signal N279 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N20 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_ne0000_7322 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_N36 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_CS_FSM_FFd1_In : STD_LOGIC; 
  signal N228 : STD_LOGIC; 
  signal N229 : STD_LOGIC; 
  signal RX_DATA_INC_02 : STD_LOGIC; 
  signal RX_DATA_INC_10 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd4_In48_7336 : STD_LOGIC; 
  signal N210 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd1_In_bdd5 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In1161_7339 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd4_In1121_7340 : STD_LOGIC; 
  signal RX_DATA_INC_06 : STD_LOGIC; 
  signal RX_DATA_INC_14 : STD_LOGIC; 
  signal RX_DATA_INC_07 : STD_LOGIC; 
  signal RX_DATA_INC_15 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_3_42_7349 : STD_LOGIC; 
  signal N232 : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_0_22_7357 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_2_49_7362 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In41_7365 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_cmp_lt0001 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_CURRENT_STATE_FSM_FFd5_In82_7374 : STD_LOGIC; 
  signal U_FIFO_BU2_U0_grf_rf_rstblk_wr_rst_comb : STD_LOGIC; 
  signal N251 : STD_LOGIC; 
  signal RESOURCE_SHARING_CONTROL_1_COUNT_CHAN : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_3_133_7380 : STD_LOGIC; 
  signal BIT_ALIGN_MACHINE_0_STORE_DATA_PREV : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd5_In233_7413 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd19 : STD_LOGIC; 
  signal DATA_TO_MACHINE_mux0000_2_77_7419 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_STATUS : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd3_In_bdd4 : STD_LOGIC; 
  signal RT_WINDOW_MONITOR_0_CURRENT_STATE_FSM_FFd2_In_bdd6 : STD_LOGIC; 
  signal RX_MON_INC_00 : STD_LOGIC; 
  signal RX_MON_INC_01 : STD_LOGIC; 
  signal RX_MON_INC_02 : STD_LOGIC; 
  signal RX_MON_INC_10 : STD_LOGIC; 
  signal RX_MON_INC_03 : STD_LOGIC; 
  signal RX_MON_INC_11 : STD_LOGIC; 
  signal RX_MON_INC_04 : STD_LOGIC; 
  signal RX_MON_INC_12 : STD_LOGIC; 
  signal RX_MON_INC_05 : STD_LOGIC; 
  signal RX_MON_INC_13 : STD_LOGIC; 
  signal RX_MON_INC_06 : STD_LOGIC; 
  signal RX_MON_INC_14 : STD_LOGIC; 
  signal RX_MON_INC_07 : STD_LOGIC; 
  signal RX_MON_INC_15 : STD_LOGIC; 
  signal RX_MON_INC_08 : STD_LOGIC; 
  signal N115 : STD_LOGIC; 
  signal N65 : STD_LOGIC; 
  signal RX_MON_INC_09 : STD_LOGIC; 
  signal N116 : STD_LOGIC; 
  signal INC_CAPTURE_3_Q : STD_LOGIC; 
  signal MONITOR_TO_RT_mux0000_1_22_7458 : STD_LOGIC; 
  signal DATA_TO_RT_mux0000_3_49_7463 : STD_LOGIC; 
  signal RX_DATA_CE_02 : STD_LOGIC; 
  signal RX_DATA_CE_06 : STD_LOGIC;