lvds_bist_top.vhd

FPGA之间的LVDS传输

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:18:52 08/25/2008 
-- Design Name: 
-- Module Name:    lvds_bist_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity lvds_bist_top is
	PORT(
		DATA_RX_P   : IN std_logic_vector(16 DOWNTO 0); -- SERIAL SIDE RX DATA (P)
      DATA_RX_N   : IN std_logic_vector(16 DOWNTO 0); -- SERIAL SIDE RX DATA (N)
		CLOCK_RX_P  : IN std_logic;   -- FORWARDED CLOCK FROM TX (P)
      CLOCK_RX_N  : IN std_logic;   -- FORWARDED CLOCK FROM TX (N)
		RXCLK          : OUT std_logic;   
      RXCLKDIV       : OUT std_logic;
      TRAINING_DONE_RX  : OUT std_logic;   -- ALIGNMENT OF ALL CHANNELS COMPLETE

		check_error	:	out std_logic;
      RESET_N           : IN std_logic;   -- RX DOMAIN RESET
		CLK_50M       : IN std_logic;		
      IDELAY_READY   : OUT std_logic;

		TRAINING_DONE_TX           : IN std_logic;
		DATA_TX_P               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (P)
      DATA_TX_N               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (N)
      CLOCK_TX_P              : OUT std_logic;   -- FORWARDED CLOCK TO RX (P)
      CLOCK_TX_N              : OUT std_logic;
		
		TAP_00     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_01     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_02     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_03     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_04     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_05     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_06     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_07     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_08     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_09     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_10     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_11     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_12     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_13     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_14     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_15     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_16     : OUT std_logic_vector(5 DOWNTO 0)); -- IDELAY TAP COUNT (0-63) 
end lvds_bist_top;

architecture Behavioral of lvds_bist_top is

COMPONENT lvds_tx_rx_merge
    PORT(DATA_RX_P   : IN std_logic_vector(16 DOWNTO 0); -- SERIAL SIDE RX DATA (P)
      DATA_RX_N   : IN std_logic_vector(16 DOWNTO 0); -- SERIAL SIDE RX DATA (N)
      CLOCK_RX_P  : IN std_logic;   -- FORWARDED CLOCK FROM TX (P)
      CLOCK_RX_N  : IN std_logic;   -- FORWARDED CLOCK FROM TX (N)
      INC_PAD     : IN std_logic;   -- MANUAL INCREMENT TO DATA DELAY
      DEC_PAD     : IN std_logic;   -- MANUAL DECREMENT TO DATA DELAY
      DATA_RX_FIFO       : OUT std_logic_vector(31 DOWNTO 0);   
      DATA_RX_FIFO_VLD    : OUT std_logic;
      RESET           : IN std_logic;   -- RX DOMAIN RESET
      IDLY_RESET        : IN std_logic;   -- IDELAY TAP RESET
      IDELAYCTRL_RESET  : IN std_logic;   -- IDELAYCTRL CIRCUIT RESET
      BITSLIP_PAD       : IN std_logic;   -- MANUAL BITSLIP TO DATA
      CLK200            : IN std_logic; -- 200 MHZ REFERENCE CLOCK TO IDELAYCTRL				
      TAP_00     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_01     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_02     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_03     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_04     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_05     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_06     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_07     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_08     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_09     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_10     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_11     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_12     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_13     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_14     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_15     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_16     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_CLK    : OUT std_logic_vector(5 DOWNTO 0); 
      TRAINING_DONE_RX  : OUT std_logic;   -- ALIGNMENT OF ALL CHANNELS COMPLETE
      RXCLK          : OUT std_logic;   
      CLK_USR       : IN std_logic;   
		RXCLKDIV       : OUT std_logic;
      IDELAY_READY   : OUT std_logic;   
      RT_MANUAL_DISABLE       : IN std_logic; 
		DATA_TX_P               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (P)
      DATA_TX_N               : OUT std_logic_vector(16 DOWNTO 0);   -- SERIAL SIDE TX DATA (N)
      CLOCK_TX_P              : OUT std_logic;   -- FORWARDED CLOCK TO RX (P)
      CLOCK_TX_N              : OUT std_logic;   -- FORWARDED CLOCK TO RX (N)
      TXCLK                   : IN std_logic;   -- SERIAL SIDE TX CLOCK
      TXCLKDIV                : IN std_logic;   -- PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
      DATA_TX_FIFO	         : IN std_logic_vector(31 DOWNTO 0);   -- PARALLEL SIDE TX DATA
      DATA_TX_FIFO_VLD	      : IN std_logic;
      DATA_TX_FIFO_RDY	      : OUT std_logic;
      --RESET                   : IN std_logic;   -- TX DOMAIN RESET
      TRAINING_DONE_TX           : IN std_logic);
    END COMPONENT;	
	 component synth_tb_lvds
	 port(
		usr_clk	: in	std_logic;
		reset		: in	std_logic;
		check_error	:	out 	std_logic;
		usr_data_tx_vld	:	out std_logic;
		usr_data_tx_rdy	:	in	std_logic;
		Data_bus_tx			:	out std_logic_vector(31 downto 0);
		usr_data_rx_vld	:	in	std_logic;	
		Data_bus_rx	:	in	std_logic_vector(31 downto 0);
		TRAINING_DONE:	in std_logic;
		blind_timer_up	: out std_logic
	 );
	 END COMPONENT;
	 
	 	 COMPONENT lvds_dcm 
	port ( CLKIN_IN        : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic;
			 CLKFX_OUT       : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          CLK2X_OUT       : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
	end COMPONENT;
	
	signal usr_data_tx_vld	:	std_logic;
	signal usr_data_tx_rdy	:	std_logic;
	signal Data_bus_tx		:	std_logic_vector(31 downto 0);
	signal usr_data_rx_vld	:	std_logic;		
	signal Data_bus_rx		:	std_logic_vector(31 downto 0);
	signal CLK_USR	:	std_logic;
	signal blind_timer_up	:	std_logic;
	 
	signal CLK_DELAY,CLK100:		std_logic;
	signal dcm_locked:		std_logic;
	signal RESET:		std_logic;
	signal RESET_r:   std_logic_vector(9 downto 0);
	
	signal CLK2X		:		std_logic;
	signal TXCLK		:		std_logic;
   signal TXCLKDIV	:		std_logic;
	 
begin

	CLK_USR<=CLK_DELAY;--200M
	TXCLKDIV <= CLK100;--100M
	TXCLK <= CLK_DELAY;--200M
	

   process(CLK100,RESET_N)
	begin
		if CLK100'event and CLK100='1' then
			RESET_r <= RESET_r(8 downto 0) & (not RESET_N);
		end if;
	end process;

	RESET <= RESET_r(9) and RESET_r(8) and RESET_r(7) and RESET_r(6) and RESET_r(5) and RESET_r(4) and RESET_r(3) and RESET_r(2) and RESET_r(1) and RESET_r(0);

	
   u_DCM: lvds_dcm
	port MAP
	( 
			CLKIN_IN  => CLK_50M,
         RST_IN    => '0',
         CLKFX_OUT  => CLK_DELAY,
         CLKIN_IBUFG_OUT => open,
         CLK0_OUT        => open,
         CLK2X_OUT       => CLK100,
         LOCKED_OUT      => dcm_locked
	);
	
	u_lvds: lvds_tx_rx_merge PORT MAP (
			 DATA_TX_FIFO	         => Data_bus_tx,  
			 DATA_TX_FIFO_VLD	      => usr_data_tx_vld,
			 DATA_TX_FIFO_RDY	      => usr_data_tx_rdy,
			 DATA_RX_FIFO       		=> Data_bus_rx, 
			 DATA_RX_FIFO_VLD   		=> usr_data_rx_vld,	
			
          DATA_RX_P => DATA_RX_P,
          DATA_RX_N => DATA_RX_N,
          CLOCK_RX_P => CLOCK_RX_P,
          CLOCK_RX_N => CLOCK_RX_N,
			 
			INC_PAD  =>'0',
			DEC_PAD  =>'0',
			BITSLIP_PAD  =>'0',
			TAP_00       =>TAP_00,
			TAP_01       =>TAP_01,
			TAP_02       =>TAP_02,
			TAP_03       =>TAP_03,
			TAP_04       =>TAP_04,
			TAP_05       =>TAP_05,
			TAP_06       =>TAP_06,
			TAP_07       =>TAP_07,
			TAP_08       =>TAP_08,
			TAP_09       =>TAP_09,
			TAP_10       =>TAP_10,
			TAP_11       =>TAP_11,
			TAP_12       =>TAP_12,
			TAP_13       =>TAP_13,
			TAP_14       =>TAP_14,
			TAP_15       =>TAP_15,
			TAP_16       =>TAP_16,
			TAP_CLK      =>open,
			TRAINING_DONE_RX =>TRAINING_DONE_RX ,
			RT_MANUAL_DISABLE=>'0', 
			TRAINING_DONE_TX =>TRAINING_DONE_TX,--tx_ready , 
          RESET => RESET,
          IDLY_RESET => RESET,
          IDELAYCTRL_RESET => RESET,
          CLK200 => CLK_DELAY,
          RXCLK => RXCLK,
			 CLK_USR => CLK_USR,
          RXCLKDIV => RXCLKDIV,
          IDELAY_READY => IDELAY_READY,
          DATA_TX_P => DATA_TX_P,
          DATA_TX_N => DATA_TX_N,
          CLOCK_TX_P => CLOCK_TX_P,
          CLOCK_TX_N => CLOCK_TX_N,
          TXCLK => TXCLK,
			 TXCLKDIV => TXCLKDIV
        );
		  
	u_tb: synth_tb_lvds PORT MAP (
          usr_clk				=>	CLK_USR,
			 reset				=>	RESET,
			 check_error		=> check_error,
			 usr_data_tx_vld	=>	usr_data_tx_vld,
			 usr_data_tx_rdy	=>	usr_data_tx_rdy,
			 Data_bus_tx		=>	Data_bus_tx,
			 usr_data_rx_vld	=>	usr_data_rx_vld,	
			 Data_bus_rx		=>	Data_bus_rx,
			 TRAINING_DONE		=> TRAINING_DONE_TX,
			 blind_timer_up	=> blind_timer_up
        );
	


end Behavioral;