test_rx.fdo

FPGA之间的LVDS传输

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Wed Aug 20 10:46:41 中国标准时间 2008
##
vlib work
vcom -explicit  -93 "seven_bit_reg_w_ce.vhd"
vcom -explicit  -93 "count_to_16x.vhd"
vcom -explicit  -93 "count_to_128.vhd"
vcom -explicit  -93 "RT_WINDOW_MONITOR.vhd"
vcom -explicit  -93 "RESOURCE_SHARING_CONTROL.vhd"
vcom -explicit  -93 "COUNT_TO_64.vhd"
vcom -explicit  -93 "BIT_ALIGN_MACHINE.vhd"
vcom -explicit  -93 "DDR_6TO1_16CHAN_RT_RX.vhd"
vcom -explicit  -93 "test_rx.vhd"
vsim -t 1ps   -lib work test_rx
do {test_rx_wave.fdo}
view wave
view structure
view signals
run 1000ns
do {test_rx.udo}