lvds_dcm_arwz.ucf

FPGA之间的LVDS传输

# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_ADV_INST CLK_FEEDBACK = 1X;
INST DCM_ADV_INST CLKDV_DIVIDE = 2.0;
INST DCM_ADV_INST CLKFX_DIVIDE = 1;
INST DCM_ADV_INST CLKFX_MULTIPLY = 4;
INST DCM_ADV_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_ADV_INST CLKIN_PERIOD = 20.000;
INST DCM_ADV_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_ADV_INST DCM_AUTOCALIBRATION = TRUE;
INST DCM_ADV_INST DCM_PERFORMANCE_MODE = MAX_SPEED;
INST DCM_ADV_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_ADV_INST DFS_FREQUENCY_MODE = HIGH;
INST DCM_ADV_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_ADV_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_ADV_INST FACTORY_JF = F0F0;
INST DCM_ADV_INST PHASE_SHIFT = 0;
INST DCM_ADV_INST STARTUP_WAIT = FALSE;
INST DCM_ADV_INST SIM_DEVICE = VIRTEX5;