lvds_bist_top_map.mrp

FPGA之间的LVDS传输

   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_12 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_04 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_13 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_05 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_14 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_06 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_15 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_07 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_08 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_09 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_00>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_01>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_10>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_02>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_11>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_03>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_12>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_04>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_13>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_05>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_14>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_06>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_15>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_07>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_08>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_DATA_09>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/IODELAY_RX_CNTL>:<IODELAY_IODELAY>.  When DELAY_SRC
   is not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_00>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_01>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_10>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_02>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_11>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_03>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_12>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_04>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_13>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_05>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_14>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_06>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_15>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_07>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_08>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_DATA_09>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_RX_CNTL>:<ISERDES_ISERDES>.  Useless CE2
   input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<u_lvds/uut_rx/ISERDES_CLOCK_RX>:<IODELAY_IODELAY>.  When
   DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
   1.050 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 182 IOs, 76 are locked
   and 106 are not locked. If you would like to print the names of these IOs,
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
INFO:Pack:1650 - Map created a placed design.
INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
   the DCM_ADV comp u_DCM/DCM_ADV_INST, consult the device Data Sheet.

Section 4 - Removed Logic Summary
---------------------------------
 100 block(s) removed
 435 block(s) optimized away
  62 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT" (ROM)
removed.
Loadless block "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DSR" (ROM) removed.
Loadless block "U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B"
(ROM) removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_00" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<0>" is loadless and has been removed.
 The signal "RXCLK_OBUF" is loadless and has been removed.
 The signal "RESET" is loadless and has been removed.
 The signal "RXCLKDIV_OBUF" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_01" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<1>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_02" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<2>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_03" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<3>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_04" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<4>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_05" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<5>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_06" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<6>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_07" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<7>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_08" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<8>" is loadless and has been removed.
Loadless block "u_lvds/uut_rx/ISERDES_RX_MON_09" () removed.
 The signal "u_lvds/uut_rx/DATA_RX_IDLY_MON<9>" is loadless and has been removed.