lvds_bist_top_map.mrp

FPGA之间的LVDS传输

Release 10.1.02 Map K.37 (nt)
Xilinx Mapping Report File for Design 'lvds_bist_top'

Design Information
------------------
Command Line   : map -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -p
xc5vfx130t-ff1738-1 -w -logic_opt off -ol high -t 1 -cm area -pr o -k 6 -lc off -power off -o lvds_bist_top_map.ncd
lvds_bist_top.ngd lvds_bist_top.pcf 
Target Device  : xc5vfx130t
Target Package : ff1738
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Sun Jan 11 22:57:10 2009

Design Summary
--------------
Number of errors:      0
Number of warnings:   65
Slice Logic Utilization:
  Number of Slice Registers:                 1,707 out of  81,920    2%
    Number used as Flip Flops:               1,707
  Number of Slice LUTs:                      1,404 out of  81,920    1%
    Number used as logic:                      943 out of  81,920    1%
      Number using O6 output only:             827
      Number using O5 output only:             112
      Number using O5 and O6:                    4
    Number used as Memory:                     435 out of  25,280    1%
      Number used as Shift Register:           435
        Number using O6 output only:           433
        Number using O5 output only:             1
        Number using O5 and O6:                  1
    Number used as exclusive route-thru:        26
  Number of route-thrus:                       139 out of 163,840    1%
    Number using O6 output only:               138
    Number using O5 output only:                 1

Slice Logic Distribution:
  Number of occupied Slices:                   857 out of  20,480    4%
  Number of LUT Flip Flop pairs used:        2,219
    Number with an unused Flip Flop:           512 out of   2,219   23%
    Number with an unused LUT:                 815 out of   2,219   36%
    Number of fully used LUT-FF pairs:         892 out of   2,219   40%
    Number of unique control sets:             132
    Number of slice register sites lost
      to control set restrictions:             305 out of  81,920    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       182 out of     840   21%
    IOB Flip Flops:                              1
    IOB Master Pads:                            18
    IOB Slave Pads:                             18

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                      26 out of     298    8%
    Number using BlockRAM only:                 26
    Total primitives used:
      Number of 36k BlockRAM used:              25
      Number of 18k BlockRAM used:               1
    Total Memory used (KB):                    918 out of  10,728    8%
  Number of BUFG/BUFGCTRLs:                      5 out of      32   15%
    Number used as BUFGs:                        3
    Number used as BUFGCTRLs:                    2
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFIOs:                              1 out of     104    1%
  Number of DCM_ADVs:                            1 out of      12    8%
  Number of ISERDESs:                           17
  Number of OSERDESs:                           17

  Number of RPM macros:            9
Peak Memory Usage:  596 MB
Total REAL time to MAP completion:  11 mins 42 secs 
Total CPU time to MAP completion:   7 mins 17 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network u_DCM/CLK0_OUT has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 8
   more times for the following (max. 5 shown):
   u_lvds/uut_tx/U_FIFO/full,
   u_lvds/uut_tx/U_FIFO/empty,
   u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<0>,
   u_lvds/uut_rx/RT_WINDOW_MONITOR_0/DATA_ALIGNED_RT,
   u_lvds/uut_rx/U_FIFO/full
   To see the details of these warning messages, please use the -detail switch.
WARNING:Pack:1186 - One or more I/O components have conflicting property values.
    For each occurrence, the system will use the property value attached to the
   pad.  Otherwise, the system will use the first property value read.  To view
   each occurrence, create a detailed map report (run map using the -detail
   option).
WARNING:Pack:2574 - The F7 multiplexer symbol
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16A/U_MUX8B/YES_LUT6.U_MUXF7" and its I1 input driver
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" were implemented
   suboptimally in the same slice component. The function generator could not be
   placed directly driving the F7 multiplexer. The design will exhibit
   suboptimal timing.
WARNING:Pack:2574 - The F7 multiplexer symbol
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16B/U_MUX8B/YES_LUT6.U_MUXF7" and its I1 input driver
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" were implemented
   suboptimally in the same slice component. The function generator could not be
   placed directly driving the F7 multiplexer. The design will exhibit
   suboptimal timing.
WARNING:Pack:2143 - The function generator
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" failed to merge with F7
   multiplexer
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16B/U_MUX8A/YES_LUT6.U_MUXF7".  There are more than two MUXF7 wide
   function muxes.  The design will exhibit suboptimal timing.
WARNING:Pack:2143 - The function generator
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" failed to merge with F7
   multiplexer
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16C/U_MUX8B/YES_LUT6.U_MUXF7".  There are more than two MUXF7 wide
   function muxes.  The design will exhibit suboptimal timing.
WARNING:Pack:2143 - The function generator
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" failed to merge with F7
   multiplexer
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16C/U_MUX8A/YES_LUT6.U_MUXF7".  There are more than two MUXF7 wide
   function muxes.  The design will exhibit suboptimal timing.
WARNING:Pack:2143 - The function generator
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" failed to merge with F7
   multiplexer
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16D/U_MUX8B/YES_LUT6.U_MUXF7".  There are more than two MUXF7 wide
   function muxes.  The design will exhibit suboptimal timing.
WARNING:Pack:2143 - The function generator
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<11>658" failed to merge with F7
   multiplexer
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16D/U_MUX8A/YES_LUT6.U_MUXF7".  There are more than two MUXF7 wide
   function muxes.  The design will exhibit suboptimal timing.
WARNING:Pack:2145 - The F7 mux
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16B/U_MUX8B/YES_LUT6.U_MUXF7" failed to merge with F8 mux
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16B/YES_LUT6.U_MUXF8".  There are more than two MUXF7 wide function
   muxes.  The design will exhibit suboptimal timing.
WARNING:Pack:2145 - The F7 mux
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16A/U_MUX8B/YES_LUT6.U_MUXF7" failed to merge with F8 mux
   "U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_
   LUT6.U_MUX16A/YES_LUT6.U_MUXF8".  There are more than two MUXF7 wide function
   muxes.  The design will exhibit suboptimal timing.
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_Cntl with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_00 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_01 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_10 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_02 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_11 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp u_lvds/uut_tx/OSERDES_TX_DATA_03 with TRISTATE_WIDTH.