uut_tx_wrapper_map.map

FPGA之间的LVDS传输

Release 10.1.02 Map K.37 (nt)
Xilinx Map Application Log File for Design 'uut_tx_wrapper'

Design Information
------------------
Command Line   : map -ise E:/ISEworks/LVDS/LVDS-func/xapp860.ise -intstyle ise
-p xc5vsx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -cm area -pr off -k 6 -lc
off -power off -o uut_tx_wrapper_map.ncd uut_tx_wrapper.ngd uut_tx_wrapper.pcf 
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Wed Aug 20 15:31:21 2008

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:e7d1) REAL time: 9 secs 

Phase 2.7
Phase 2.7 (Checksum:e7d1) REAL time: 10 secs 

Phase 3.31
Phase 3.31 (Checksum:e7d1) REAL time: 10 secs 

Phase 4.33
Phase 4.33 (Checksum:e7d1) REAL time: 10 secs 

Phase 5.32
Phase 5.32 (Checksum:e7d1) REAL time: 10 secs 

Phase 6.2
...
.
Phase 6.2 (Checksum:460ac) REAL time: 12 secs 

Phase 7.30
Phase 7.30 (Checksum:460ac) REAL time: 12 secs 

Phase 8.3
...
Phase 8.3 (Checksum:4cfa3) REAL time: 13 secs 

Phase 9.5
Phase 9.5 (Checksum:4cfa3) REAL time: 13 secs 

Phase 10.8
.
Phase 10.8 (Checksum:cbe01) REAL time: 13 secs 

Phase 11.29
Phase 11.29 (Checksum:cbe01) REAL time: 13 secs 

Phase 12.5
Phase 12.5 (Checksum:cbe01) REAL time: 13 secs 

Phase 13.18
Phase 13.18 (Checksum:cd577) REAL time: 15 secs 

Phase 14.5
Phase 14.5 (Checksum:cd577) REAL time: 15 secs 

Phase 15.34
Phase 15.34 (Checksum:cd577) REAL time: 15 secs 

REAL time consumed by placer: 15 secs 
CPU  time consumed by placer: 12 secs 

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   17
Slice Logic Utilization:
  Number of Slice Registers:                    96 out of  32,640    1%
    Number used as Flip Flops:                  96
  Number of Slice LUTs:                         48 out of  32,640    1%
    Number used as logic:                       48 out of  32,640    1%
      Number using O6 output only:              48

Slice Logic Distribution:
  Number of occupied Slices:                    71 out of   8,160    1%
  Number of LUT Flip Flop pairs used:           96
    Number with an unused Flip Flop:             0 out of      96    0%
    Number with an unused LUT:                  48 out of      96   50%
    Number of fully used LUT-FF pairs:          48 out of      96   50%
    Number of unique control sets:              49
    Number of slice register sites lost
      to control set restrictions:             144 out of  32,640    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       134 out of     480   27%
    IOB Flip Flops:                              1
    IOB Master Pads:                            17
    IOB Slave Pads:                             17

Specific Feature Utilization:
  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%
    Number used as BUFGs:                        2
  Number of OSERDESs:                           16

Peak Memory Usage:  365 MB
Total REAL time to MAP completion:  30 secs 
Total CPU time to MAP completion:   24 secs 

Mapping completed.
See MAP report file "uut_tx_wrapper_map.mrp" for details.