lvds_bist_top.syr

来自「FPGA之间的LVDS传输」· SYR 代码 · 共 588 行 · 第 1/5 页

SYR
588 行
字号
12345
    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_05> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1755: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1755: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1755: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1755: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1755: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_06> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1782: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1782: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1782: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1782: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1782: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_07> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1809: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1809: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1809: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1809: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1809: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_08> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1836: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1836: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1836: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1836: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1836: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_09> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1863: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1863: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1863: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1863: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1863: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_10> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1890: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1890: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1890: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1890: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1890: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_11> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1917: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1917: Unconnected output port 'Q2' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1917: Unconnected output port 'SHIFTOUT1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1917: Unconnected output port 'SHIFTOUT2' of component 'ISERDES_NODELAY'.WARNING:Xst:2211 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1917: Instantiating black box module <ISERDES_NODELAY>.    Set user-defined property "BITSLIP_ENABLE =  TRUE" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_RATE =  DDR" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "DATA_WIDTH =  4" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q1 =  0" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q2 =  0" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q3 =  0" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INIT_Q4 =  0" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "INTERFACE_TYPE =  NETWORKING" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "NUM_CE =  1" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.    Set user-defined property "SERDES_MODE =  MASTER" for instance <ISERDES_RX_DATA_12> in unit <DDR_6TO1_16CHAN_RT_RX>.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" line 1944: Unconnected output port 'Q1' of component 'ISERDES_NODELAY'.WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN
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lvds_bist_top.syr - 源码说明

本页面展示了「FPGA之间的LVDS传输」中的 lvds_bist_top.syr 源码文件，采用 SYR 编程语言编写，共 588 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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