lvds_bist_top.syr

来自「FPGA之间的LVDS传输」· SYR 代码 · 共 588 行 · 第 1/5 页

WARNING:HDLParsers:3607 - Unit work/DDR_6TO1_16CHAN_RT_RX/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd".
WARNING:HDLParsers:3607 - Unit work/DDR_6TO1_16CHAN_RT_TX is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/DDR_6TO1_16CHAN_RT_TX.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_TX.vhd".
WARNING:HDLParsers:3607 - Unit work/DDR_6TO1_16CHAN_RT_TX/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/DDR_6TO1_16CHAN_RT_TX.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_TX.vhd".
WARNING:HDLParsers:3607 - Unit work/BIT_ALIGN_MACHINE is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/BIT_ALIGN_MACHINE.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.vhd".
WARNING:HDLParsers:3607 - Unit work/BIT_ALIGN_MACHINE/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/BIT_ALIGN_MACHINE.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.vhd".
WARNING:HDLParsers:3607 - Unit work/COUNT_TO_64 is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/COUNT_TO_64.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/COUNT_TO_64.vhd".
WARNING:HDLParsers:3607 - Unit work/COUNT_TO_64/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/COUNT_TO_64.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/COUNT_TO_64.vhd".
WARNING:HDLParsers:3607 - Unit work/fifo_rx is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/fifo_rx.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/fifo_rx.vhd".
WARNING:HDLParsers:3607 - Unit work/fifo_rx/fifo_rx_a is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/fifo_rx.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/fifo_rx.vhd".
WARNING:HDLParsers:3607 - Unit work/fifo_tx is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/fifo_tx.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/fifo_tx.vhd".
WARNING:HDLParsers:3607 - Unit work/fifo_tx/fifo_tx_a is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/fifo_tx.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/fifo_tx.vhd".
WARNING:HDLParsers:3607 - Unit work/RESOURCE_SHARING_CONTROL is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/RESOURCE_SHARING_CONTROL.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RESOURCE_SHARING_CONTROL.vhd".
WARNING:HDLParsers:3607 - Unit work/RESOURCE_SHARING_CONTROL/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/RESOURCE_SHARING_CONTROL.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RESOURCE_SHARING_CONTROL.vhd".
WARNING:HDLParsers:3607 - Unit work/RT_WINDOW_MONITOR is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/RT_WINDOW_MONITOR.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RT_WINDOW_MONITOR.vhd".
WARNING:HDLParsers:3607 - Unit work/RT_WINDOW_MONITOR/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/RT_WINDOW_MONITOR.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RT_WINDOW_MONITOR.vhd".
WARNING:HDLParsers:3607 - Unit work/count_to_128 is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/count_to_128.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/count_to_128.vhd".
WARNING:HDLParsers:3607 - Unit work/count_to_128/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/count_to_128.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/count_to_128.vhd".
WARNING:HDLParsers:3607 - Unit work/count_to_16x is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/count_to_16x.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/count_to_16x.vhd".
WARNING:HDLParsers:3607 - Unit work/count_to_16x/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/count_to_16x.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/count_to_16x.vhd".
WARNING:HDLParsers:3607 - Unit work/seven_bit_reg_w_ce is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/seven_bit_reg_w_ce.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/seven_bit_reg_w_ce.vhd".
WARNING:HDLParsers:3607 - Unit work/seven_bit_reg_w_ce/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/seven_bit_reg_w_ce.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/seven_bit_reg_w_ce.vhd".
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/count_to_128.vhd" in Library work.
Architecture translated of Entity count_to_128 is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/seven_bit_reg_w_ce.vhd" in Library work.
Architecture translated of Entity seven_bit_reg_w_ce is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/count_to_16x.vhd" in Library work.
Architecture translated of Entity count_to_16x is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/fifo_tx.vhd" in Library work.
Architecture fifo_tx_a of Entity fifo_tx is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/fifo_rx.vhd" in Library work.
Architecture fifo_rx_a of Entity fifo_rx is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RESOURCE_SHARING_CONTROL.vhd" in Library work.
Architecture translated of Entity resource_sharing_control is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/BIT_ALIGN_MACHINE.vhd" in Library work.
Architecture translated of Entity bit_align_machine is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RT_WINDOW_MONITOR.vhd" in Library work.
Architecture translated of Entity rt_window_monitor is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/COUNT_TO_64.vhd" in Library work.
Architecture translated of Entity count_to_64 is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd" in Library work.
Architecture translated of Entity ddr_6to1_16chan_rt_rx is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_TX.vhd" in Library work.
Architecture translated of Entity ddr_6to1_16chan_rt_tx is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_dcm.vhd" in Library work.
Architecture behavioral of Entity lvds_dcm is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_tx_rx_merge.vhd" in Library work.
Architecture translated of Entity lvds_tx_rx_merge is up to date.
Compiling vhdl file "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_bist_top.vhd" in Library work.
Architecture behavioral of Entity lvds_bist_top is up to date.
Compiling verilog file "synth_tb_lvds.v" in library work
Module <synth_tb_lvds> compiled
No errors in compilation
Analysis of file <"lvds_bist_top.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <lvds_bist_top> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <lvds_dcm> in library <work> (architecture <behavioral>).

Analyzing hierarchy for entity <lvds_tx_rx_merge> in library <work> (architecture <translated>).

Analyzing hierarchy for module <synth_tb_lvds> in library <work>.

Analyzing hierarchy for entity <DDR_6TO1_16CHAN_RT_RX> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <DDR_6TO1_16CHAN_RT_TX> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <RESOURCE_SHARING_CONTROL> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <BIT_ALIGN_MACHINE> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <RT_WINDOW_MONITOR> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <COUNT_TO_64> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <count_to_128> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <count_to_16x> in library <work> (architecture <translated>).

Analyzing hierarchy for entity <seven_bit_reg_w_ce> in library <work> (architecture <translated>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lvds_bist_top> in library <work> (Architecture <behavioral>).
WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_bist_top.vhd" line 181: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'lvds_dcm'.
WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_bist_top.vhd" line 181: Unconnected output port 'CLK0_OUT' of component 'lvds_dcm'.
WARNING:Xst:753 - "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_bist_top.vhd" line 193: Unconnected output port 'TAP_CLK' of component 'lvds_tx_rx_merge'.
Entity <lvds_bist_top> analyzed. Unit <lvds_bist_top> generated.

Analyzing Entity <lvds_dcm> in library <work> (Architecture <behavioral>).
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <lvds_dcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <lvds_dcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <lvds_dcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "CLKIN_PERIOD =  20.0000000000000000" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  HIGH" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "FACTORY_JF =  F0F0" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "SIM_DEVICE =  VIRTEX5" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_ADV_INST> in unit <lvds_dcm>.
Entity <lvds_dcm> analyzed. Unit <lvds_dcm> generated.

Analyzing Entity <lvds_tx_rx_merge> in library <work> (Architecture <translated>).