lvds_bist_top.syr

来自「FPGA之间的LVDS传输」· SYR 代码 · 共 588 行 · 第 1/5 页

Release 10.1.02 - xst K.37 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xst/projnav.tmp


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.44 secs
 
--> Parameter xsthdpdir set to E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xst


Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.44 secs
 
--> Reading design: lvds_bist_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lvds_bist_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lvds_bist_top"
Output Format                      : NGC
Target Device                      : xc5vfx130t-1-ff1738

---- Source Options
Top Module Name                    : lvds_bist_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Use DSP Block                      : auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : off
Reduce Control Sets                : off
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Library Search Order               : lvds_bist_top.lso
Keep Hierarchy                     : YES
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3607 - Unit work/lvds_bist_top is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_bist_top.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_bist_top.vhd".
WARNING:HDLParsers:3607 - Unit work/lvds_bist_top/Behavioral is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_bist_top.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_bist_top.vhd".
WARNING:HDLParsers:3607 - Unit work/lvds_dcm is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_dcm.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_dcm.vhd".
WARNING:HDLParsers:3607 - Unit work/lvds_dcm/BEHAVIORAL is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_dcm.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_dcm.vhd".
WARNING:HDLParsers:3607 - Unit work/lvds_tx_rx_merge is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_tx_rx_merge.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_tx_rx_merge.vhd".
WARNING:HDLParsers:3607 - Unit work/lvds_tx_rx_merge/translated is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_tx_rx_merge.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_tx_rx_merge.vhd".
WARNING:HDLParsers:3607 - Unit work/DDR_6TO1_16CHAN_RT_RX is now defined in a different file.  It was defined in "E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd", and is now defined in "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd".