📄 lvds_bist_top_map.map
字号:
Release 10.1.02 Map K.37 (nt)Xilinx Map Application Log File for Design 'lvds_bist_top'Design Information------------------Command Line : map -ise
E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle
ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high -t 1 -cm area -pr o -k 6
-lc off -power off -o lvds_bist_top_map.ncd lvds_bist_top.ngd lvds_bist_top.pcf Target Device : xc5vfx130tTarget Package : ff1738Target Speed : -1Mapper Version : virtex5 -- $Revision: 1.46.12.2 $Mapped Date : Sun Jan 11 22:57:10 2009Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).Running timing-driven packing...Phase 1.1Phase 1.1 (Checksum:13a7356) REAL time: 1 mins 34 secs Phase 2.7INFO:Place:834 - Only a subset of IOs are locked. Out of 182 IOs, 76 are locked
and 106 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. Phase 2.7 (Checksum:13a7356) REAL time: 1 mins 40 secs Phase 3.31Phase 3.31 (Checksum:172e677) REAL time: 1 mins 40 secs Phase 4.33Phase 4.33 (Checksum:172e677) REAL time: 2 mins 22 secs Phase 5.32Phase 5.32 (Checksum:172e677) REAL time: 2 mins 26 secs Phase 6.2....There are 20 clock regions on the target FPGA device:|------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y9: | CLOCKREGION_X1Y9: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 4 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y8: | CLOCKREGION_X1Y8: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 4 center BUFIOs available, 1 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y7: | CLOCKREGION_X1Y7: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 0 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y6: | CLOCKREGION_X1Y6: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 2 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y5: | CLOCKREGION_X1Y5: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 2 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 2 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 2 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 0 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 4 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|| CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: || 2 BUFRs available, 0 in use | 2 BUFRs available, 0 in use || 4 Regional Clock Spines, 0 in use | 4 Regional Clock Spines, 0 in use || 4 edge BUFIOs available, 0 in use | 4 edge BUFIOs available, 0 in use || 4 center BUFIOs available, 0 in use | || | ||------------------------------------------|------------------------------------------|Clock-Region: <CLOCKREGION_X0Y8> key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 1/4; bufrs - 0/2; regional-clock-spines - 0/4|-----------------------------------------------------------------------------------------------------------------------------------------------------------| | clock | BRAM | | | | | | | | | | | || | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------| | Upper Region| 20 | 0 | 0 | 80 | 80 | 5120 | 3040 | 7200 | 16 | 0 | 0 | 0 | <- Available resources in the upper region|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------| |CurrentRegion| 20 | 0 | 0 | 80 | 80 | 5120 | 3040 | 7200 | 16 | 0 | 0 | 0 | <- Available resources in the current region|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------| | Lower Region| 12 | 4 | 0 | 40 | 40 | 3200 | 2080 | 4320 | 16 | 0 | 0 | 0 | <- Available resources in the lower region|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------| clock | region | -----------------------------------------------| type | expansion | | <IO/Regional clock Net Name>|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------| BUFIO | | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | "u_lvds/uut_rx/RXCLK_TEMP"|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------####################################################################################### REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:## Number of Regional Clocking Regions in the device: 20 (4 clock spines in each)# Number of Regional Clock Networks used in this design: 1 (each network can be# composed of up to 3 clock spines and cover up to 3 regional clock regions)# ####################################################################################### IO-Clock "u_lvds/uut_rx/RXCLK_TEMP" driven by "BUFIO_X1Y33"INST "u_lvds/uut_rx/RX_CLK_BUFIO" LOC = "BUFIO_X1Y33" ;NET "u_lvds/uut_rx/RXCLK_TEMP" TNM_NET = "TN_u_lvds/uut_rx/RXCLK_TEMP" ;TIMEGRP "TN_u_lvds/uut_rx/RXCLK_TEMP" AREA_GROUP = "CLKAG_u_lvds/uut_rx/RXCLK_TEMP" ;AREA_GROUP "CLKAG_u_lvds/uut_rx/RXCLK_TEMP" RANGE = CLOCKREGION_X0Y8;Phase 6.2 (Checksum:17fd111) REAL time: 2 mins 56 secs Phase 7.30Phase 7.30 (Checksum:17fd111) REAL time: 2 mins 56 secs Phase 8.3...Phase 8.3 (Checksum:2904516) REAL time: 2 mins 58 secs Phase 9.5Phase 9.5 (Checksum:2904516) REAL time: 2 mins 59 secs Phase 10.8......................................................................................Phase 10.8 (Checksum:24e4d28b) REAL time: 3 mins 14 secs Phase 11.29Phase 11.29 (Checksum:24e4d28b) REAL time: 3 mins 14 secs Phase 12.5Phase 12.5 (Checksum:24e4d28b) REAL time: 3 mins 14 secs Phase 13.18Phase 13.18 (Checksum:251a0648) REAL time: 9 mins 1 secs Phase 14.5Phase 14.5 (Checksum:251a0648) REAL time: 9 mins 1 secs Phase 15.34Phase 15.34 (Checksum:251a0648) REAL time: 9 mins 2 secs REAL time consumed by placer: 9 mins 4 secs CPU time consumed by placer: 6 mins 20 secs Design Summary--------------Design Summary:Number of errors: 0Number of warnings: 65Slice Logic Utilization: Number of Slice Registers: 1,707 out of 81,920 2% Number used as Flip Flops: 1,707 Number of Slice LUTs: 1,404 out of 81,920 1% Number used as logic: 943 out of 81,920 1% Number using O6 output only: 827 Number using O5 output only: 112 Number using O5 and O6: 4 Number used as Memory: 435 out of 25,280 1% Number used as Shift Register: 435 Number using O6 output only: 433 Number using O5 output only: 1 Number using O5 and O6: 1 Number used as exclusive route-thru: 26 Number of route-thrus: 139 out of 163,840 1% Number using O6 output only: 138 Number using O5 output only: 1Slice Logic Distribution: Number of occupied Slices: 857 out of 20,480 4% Number of LUT Flip Flop pairs used: 2,219 Number with an unused Flip Flop: 512 out of 2,219 23% Number with an unused LUT: 815 out of 2,219 36% Number of fully used LUT-FF pairs: 892 out of 2,219 40% Number of unique control sets: 132 Number of slice register sites lost to control set restrictions: 305 out of 81,920 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails.IO Utilization: Number of bonded IOBs: 182 out of 840 21% IOB Flip Flops: 1 IOB Master Pads: 18 IOB Slave Pads: 18Specific Feature Utilization: Number of BlockRAM/FIFO: 26 out of 298 8% Number using BlockRAM only: 26 Total primitives used: Number of 36k BlockRAM used: 25 Number of 18k BlockRAM used: 1 Total Memory used (KB): 918 out of 10,728 8% Number of BUFG/BUFGCTRLs: 5 out of 32 15% Number used as BUFGs: 3 Number used as BUFGCTRLs: 2 Number of BSCANs: 1 out of 4 25% Number of BUFIOs: 1 out of 104 1% Number of DCM_ADVs: 1 out of 12 8% Number of ISERDESs: 17 Number of OSERDESs: 17 Number of RPM macros: 9Peak Memory Usage: 596 MBTotal REAL time to MAP completion: 11 mins 42 secs Total CPU time to MAP completion: 7 mins 17 secs Mapping completed.See MAP report file "lvds_bist_top_map.mrp" for details.⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -