lvds_bist_top_tb.vhd

FPGA之间的LVDS传输

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   20:56:20 08/25/2008
-- Design Name:   
-- Module Name:   E:/ISEworks/LVDS/LVDS_4to1/lvds_bist_top_tb.vhd
-- Project Name:  xapp860
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: lvds_bist_top
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY lvds_bist_top_tb IS
END lvds_bist_top_tb;
 
ARCHITECTURE behavior OF lvds_bist_top_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT lvds_bist_top
    PORT(
         DATA_RX_P : IN  std_logic_vector(16 downto 0);
         DATA_RX_N : IN  std_logic_vector(16 downto 0);
         CLOCK_RX_P : IN  std_logic;
         CLOCK_RX_N : IN  std_logic;
         check_error : OUT  std_logic;
         RESET_N : IN  std_logic;
--         IDLY_RESET : IN  std_logic;
--         IDELAYCTRL_RESET : IN  std_logic;
--         BITSLIP_PAD : IN  std_logic;
--         CLK200 : IN  std_logic;
--         TAP_00 : OUT  std_logic_vector(5 downto 0);
--         TAP_01 : OUT  std_logic_vector(5 downto 0);
--         TAP_02 : OUT  std_logic_vector(5 downto 0);
--         TAP_03 : OUT  std_logic_vector(5 downto 0);
--         TAP_04 : OUT  std_logic_vector(5 downto 0);
--         TAP_05 : OUT  std_logic_vector(5 downto 0);
--         TAP_06 : OUT  std_logic_vector(5 downto 0);
--         TAP_07 : OUT  std_logic_vector(5 downto 0);
--         TAP_08 : OUT  std_logic_vector(5 downto 0);
--         TAP_09 : OUT  std_logic_vector(5 downto 0);
--         TAP_10 : OUT  std_logic_vector(5 downto 0);
--         TAP_11 : OUT  std_logic_vector(5 downto 0);
--         TAP_12 : OUT  std_logic_vector(5 downto 0);
--         TAP_13 : OUT  std_logic_vector(5 downto 0);
--         TAP_14 : OUT  std_logic_vector(5 downto 0);
--         TAP_15 : OUT  std_logic_vector(5 downto 0);
--         TAP_16 : OUT  std_logic_vector(5 downto 0);
--         TAP_CLK : OUT  std_logic_vector(5 downto 0);
         TRAINING_DONE_RX : OUT  std_logic;
         RXCLK : OUT  std_logic;
         RXCLKDIV : OUT  std_logic;
         CLK_USR : IN  std_logic;
         IDELAY_READY : OUT  std_logic;
--         INC_PAD : IN  std_logic;
--         DEC_PAD : IN  std_logic;
--         RT_MANUAL_DISABLE : IN  std_logic;
         TRAINING_DONE_TX : IN  std_logic;
         DATA_TX_P : OUT  std_logic_vector(16 downto 0);
         DATA_TX_N : OUT  std_logic_vector(16 downto 0);
         CLOCK_TX_P : OUT  std_logic;
         CLOCK_TX_N : OUT  std_logic
--         TXCLK : IN  std_logic;
--         TXCLKDIV : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal DATA_RX_P : std_logic_vector(16 downto 0) := (others => '1');
   signal DATA_RX_N : std_logic_vector(16 downto 0) := (others => '0');
   signal CLOCK_RX_P : std_logic := '1';
   signal CLOCK_RX_N : std_logic := '0';
   signal RESET_N : std_logic := '0';
   signal CLK_USR : std_logic := '0';
   signal TRAINING_DONE_TX : std_logic := '0';

 	--Outputs
   signal check_error : std_logic;
   signal TRAINING_DONE_RX : std_logic;
   signal RXCLK : std_logic;
   signal RXCLKDIV : std_logic;
   signal IDELAY_READY : std_logic;
   signal DATA_TX_P : std_logic_vector(16 downto 0);
   signal DATA_TX_N : std_logic_vector(16 downto 0);
   signal CLOCK_TX_P : std_logic;
   signal CLOCK_TX_N : std_logic;
 
	constant CLK_USR_period:time := 21 ns;
	
--	constant delay1:time := (100010+1000) ps;
--	constant delay2:time := (100512+1000) ps;
--	constant delay3:time := (100005+1000) ps;
--	constant delay4:time := (99497+1000) ps;
--	constant delay5:time := (100512+1000) ps;
--	constant delay6:time := (100008+1000) ps;
--	constant delay7:time := (99497+1000) ps;
--	constant delay8:time := (100000+1000) ps;
--	constant delay9:time := (100000+1000) ps;
--	constant delay10:time := (100000+1000) ps;
--	constant delay11:time := (99497+1000) ps;
--	constant delay12:time := (100000+1000) ps;
--	constant delay13:time := (99890+1000) ps;
--	constant delay14:time := (100512+1000) ps;
--	constant delay15:time := (100000+1000) ps;
--	constant delay16:time := (99995+1000) ps;
--	constant delay17:time := (100512+1000) ps;
	constant delay1:time := 99510 ps;
	constant delay2:time := 99505 ps;--99512 ps;
	constant delay3:time := 99505 ps;
	constant delay4:time := 99997 ps;
	constant delay5:time := 99912 ps;
	constant delay6:time := 99508 ps;
	constant delay7:time := 99997 ps;
	constant delay8:time := 99500 ps;
	constant delay9:time := 99500 ps;
	constant delay10:time :=99500 ps;
	constant delay11:time :=99997 ps;
	constant delay12:time :=99500 ps;
	constant delay13:time :=99890 ps;
	constant delay14:time :=99512 ps;
	constant delay15:time :=99500 ps;
	constant delay16:time :=99595 ps;
	constant delay17:time :=99512 ps;
BEGIN
 
	TRAINING_DONE_TX<=TRAINING_DONE_RX;
	-- Instantiate the Unit Under Test (UUT)
   uut: lvds_bist_top PORT MAP (
          DATA_RX_P => DATA_RX_P,
          DATA_RX_N => DATA_RX_N,
          CLOCK_RX_P => CLOCK_RX_P,
          CLOCK_RX_N => CLOCK_RX_N,
          check_error => check_error,
          RESET_N => RESET_N,
          TRAINING_DONE_RX => TRAINING_DONE_RX,
          RXCLK => RXCLK,
          RXCLKDIV => RXCLKDIV,
          CLK_USR => CLK_USR,
          IDELAY_READY => IDELAY_READY,
          TRAINING_DONE_TX => TRAINING_DONE_TX,
          DATA_TX_P => DATA_TX_P,
          DATA_TX_N => DATA_TX_N,
          CLOCK_TX_P => CLOCK_TX_P,
          CLOCK_TX_N => CLOCK_TX_N
        );
 
--   CLK200_process :process
--   begin
--		CLK200 <= '0';
--		wait for (CLK200_period/2);
--		CLK200 <= '1';
--		wait for (CLK200_period/2);
--   end process;
--  
--   TXCLK_process :process
--   begin
--		TXCLK <= '0';
--		wait for (TXCLK_period/2);
--		TXCLK <= '1';
--		wait for (TXCLK_period/2);
--   end process;
--	
--	TXCLKDIV_process :process
--   begin
--		TXCLKDIV <= '0';
--		wait for (TXCLKDIV_period/2);
--		TXCLKDIV <= '1';
--		wait for (TXCLKDIV_period/2);
--   end process;
--	
	RXCLK_USR_process :process
   begin
		CLK_USR <= '0';
		wait for (CLK_USR_period/2);
		CLK_USR <= '1';
		wait for (CLK_USR_period/2);
   end process;
	
	
	--DATA_RX_P(0) <= TRANSPORT DATA_TX_P(0) after delay1 ;
	--DATA_RX_N(0) <= TRANSPORT DATA_TX_N(0) after delay1 ;
	----------------------------------------------------
	DATA_RX_P(1) <= TRANSPORT DATA_TX_P(1) after delay2 ;
	DATA_RX_N(1) <= TRANSPORT DATA_TX_N(1) after delay2 ;
	----------------------------------------------------
	DATA_RX_P(2) <= TRANSPORT DATA_TX_P(2) after delay3 ;
	DATA_RX_N(2) <= TRANSPORT DATA_TX_N(2) after delay3 ;
	----------------------------------------------------
	DATA_RX_P(3) <= TRANSPORT DATA_TX_P(3) after delay4 ;
	DATA_RX_N(3) <= TRANSPORT DATA_TX_N(3) after delay4 ;
	----------------------------------------------------
	DATA_RX_P(4) <= TRANSPORT DATA_TX_P(4) after delay5 ;
	DATA_RX_N(4) <= TRANSPORT DATA_TX_N(4) after delay5 ;
	----------------------------------------------------
	DATA_RX_P(5) <= TRANSPORT DATA_TX_P(5) after delay6 ;
	DATA_RX_N(5) <= TRANSPORT DATA_TX_N(5) after delay6 ;
	----------------------------------------------------
	DATA_RX_P(6) <= TRANSPORT DATA_TX_P(6) after delay7 ;
	DATA_RX_N(6) <= TRANSPORT DATA_TX_N(6) after delay7 ;
	----------------------------------------------------
	DATA_RX_P(7) <= TRANSPORT DATA_TX_P(7) after delay8 ;
	DATA_RX_N(7) <= TRANSPORT DATA_TX_N(7) after delay8 ;
	----------------------------------------------------
	DATA_RX_P(8) <= TRANSPORT DATA_TX_P(8) after delay9 ;
	DATA_RX_N(8) <= TRANSPORT DATA_TX_N(8) after delay9 ;
	----------------------------------------------------
	--DATA_RX_P(9) <= TRANSPORT DATA_TX_P(9) after delay10;
	--DATA_RX_N(9) <= TRANSPORT DATA_TX_N(9) after delay10;
	----------------------------------------------------
	DATA_RX_P(10) <= TRANSPORT DATA_TX_P(10) after delay11 ;
	DATA_RX_N(10) <= TRANSPORT DATA_TX_N(10) after delay11 ;
	----------------------------------------------------
	DATA_RX_P(11) <= TRANSPORT DATA_TX_P(11) after delay12 ;
	DATA_RX_N(11) <= TRANSPORT DATA_TX_N(11) after delay12 ;
	----------------------------------------------------
	DATA_RX_P(12) <= TRANSPORT DATA_TX_P(12) after delay13 ;
	DATA_RX_N(12) <= TRANSPORT DATA_TX_N(12) after delay13 ;
	----------------------------------------------------
	DATA_RX_P(13) <= TRANSPORT DATA_TX_P(13) after delay14 ;
	DATA_RX_N(13) <= TRANSPORT DATA_TX_N(13) after delay14 ;
	----------------------------------------------------
	DATA_RX_P(14) <= TRANSPORT DATA_TX_P(14) after delay15 ;
	DATA_RX_N(14) <= TRANSPORT DATA_TX_N(14) after delay15 ;
	----------------------------------------------------
	DATA_RX_P(15) <= TRANSPORT DATA_TX_P(15) after delay16 ;
	DATA_RX_N(15) <= TRANSPORT DATA_TX_N(15) after delay16 ;
	----------------------------------------------------
	DATA_RX_P(16) <= TRANSPORT DATA_TX_P(16) after delay17 ;
	DATA_RX_N(16) <= TRANSPORT DATA_TX_N(16) after delay17 ;
	----------------------------------------------------
	CLOCK_RX_P <= TRANSPORT CLOCK_TX_P after 100 ns;
   CLOCK_RX_N <= TRANSPORT CLOCK_TX_N after 100 ns;
	
	  -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 1ms.
      
		wait for 1 us;
		RESET_N <= '1';

      -- insert stimulus here 

      wait;
   end process;

END;