smartpreview.twr

FPGA之间的LVDS传输

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

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  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
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  TS_CLK_DELAY = PERIOD TIMEGRP "CLK_DELAY" | SETUP   |     0.044ns|     4.956ns|       0|           0
   5 ns HIGH 50%                            | HOLD    |     0.180ns|            |       0|           0
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  TS_CLK100 = PERIOD TIMEGRP "CLK100" 10 ns | SETUP   |     4.532ns|     5.468ns|       0|           0
   HIGH 50%                                 | HOLD    |     0.324ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.