synth_tb_lvds.v

FPGA之间的LVDS传输

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:11:43 04/14/2008 
// Design Name: 
// Module Name:    synth_tb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module synth_tb_lvds(
		usr_clk,		
      reset,		
      check_error,

		usr_data_tx_vld,	
		usr_data_tx_rdy,	
		Data_bus_tx,		

		usr_data_rx_vld,	
		Data_bus_rx,
		
		TRAINING_DONE,//TX
		blind_timer_up
);



  input			usr_clk;
  input        reset;
  output reg 	check_error;
  
  //TX
  output	reg				usr_data_tx_vld;
  input						usr_data_tx_rdy;
  output	reg	  [0:31]	Data_bus_tx;
  //RX
  input						usr_data_rx_vld;
  input		  [0:31]		Data_bus_rx;
  
  input						TRAINING_DONE;
  output reg				blind_timer_up;
  

  reg [0:31]   Data_bus_rx_check;
  reg	 [0:31]  Data_bus_rx_reg;
  
  reg			   usr_data_rx_vld_reg;
  reg				check_data_error;
  
  reg  [0:15]	 blind_timer_cnt;
  reg TRAINING_DONE_reg,TRAINING_DONE_reg2;  
  
  //wire [0:55]  Data_bus_rx_check_i;
  //wire [0:55]  Data_bus_rx_reg_i;
  reg  [9:0]   ShiftReg;
  wire         RandEn;
	
	always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				begin
					TRAINING_DONE_reg <= 1'b0;
					TRAINING_DONE_reg2 <= 1'b0;
				end	
			else
				begin
					TRAINING_DONE_reg <= TRAINING_DONE;
					TRAINING_DONE_reg2 <= TRAINING_DONE_reg;
				end
		end
	
	always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				blind_timer_up <= 1'b0;
			else if(blind_timer_cnt>13000)
				blind_timer_up <= 1'b1;
		end
	
	always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				blind_timer_cnt <= 16'h0000;
			else if(~blind_timer_up)
				blind_timer_cnt <= blind_timer_cnt + 1;
			else
				blind_timer_cnt <= blind_timer_cnt;
		end
	//TX
	always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				Data_bus_rx_reg <= 32'h0000_0000;
			else
				Data_bus_rx_reg <= Data_bus_rx;
		end
		
	always@(posedge usr_clk)// or posedge reset)
		begin
			if(reset)
				usr_data_rx_vld_reg <= 1'b0;
			else
				usr_data_rx_vld_reg <= usr_data_rx_vld;
		end
	
	
	always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				usr_data_tx_vld <= 1'b0;
			else 
				usr_data_tx_vld <= usr_data_tx_rdy & RandEn;
		end
	
	always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				Data_bus_tx <= 32'h00000_000;
			else if(usr_data_tx_vld )
				Data_bus_tx <= Data_bus_tx +1;
			else
				Data_bus_tx <= Data_bus_tx;
		end
	//RX
	
		always@(posedge usr_clk or posedge reset)
		begin
			if(reset)
				Data_bus_rx_check <=  32'h00000_000;
			else if(usr_data_rx_vld_reg)
				Data_bus_rx_check <= Data_bus_rx_check + 1;
			else
				Data_bus_rx_check <= Data_bus_rx_check;
		end	
		
		//assign  Data_bus_rx_check_i={Data_bus_rx_check[0:23],Data_bus_rx_check[28:59]};
		//assign  Data_bus_rx_reg_i  ={Data_bus_rx_reg[0:23],Data_bus_rx_reg[28:59]};
  
		always@(posedge usr_clk or posedge reset) 
		begin
			if(reset)
				check_data_error <= 1'b0;
			else if(usr_data_rx_vld_reg & (Data_bus_rx_check != Data_bus_rx_reg))
				check_data_error <= 1'b1;
			else
				check_data_error <= 1'b0;
		end


		always@(posedge usr_clk or posedge reset) 
		begin
			if(reset)
				check_error <= 1'b0;
			else if(check_error)
				check_error <= 1'b1;
			else
				check_error<= check_data_error;
		end
		
		always@(posedge usr_clk or posedge reset) 
		begin
			if(reset) 
				ShiftReg<=10'b0000000001;
			else 
				ShiftReg<={ShiftReg[8:0],ShiftReg[9]^ShiftReg[6]};
		end
	
	   assign RandEn=(ShiftReg>10'h20)?1:0;

endmodule