lvds_bist_top.prj

FPGA之间的LVDS传输

vhdl work "seven_bit_reg_w_ce.vhd"
vhdl work "count_to_16x.vhd"
vhdl work "count_to_128.vhd"
vhdl work "RT_WINDOW_MONITOR.vhd"
vhdl work "RESOURCE_SHARING_CONTROL.vhd"
vhdl work "fifo_tx.vhd"
vhdl work "fifo_rx.vhd"
vhdl work "COUNT_TO_64.vhd"
vhdl work "BIT_ALIGN_MACHINE.vhd"
vhdl work "DDR_6TO1_16CHAN_RT_TX.vhd"
vhdl work "DDR_6TO1_16CHAN_RT_RX.vhd"
verilog work "synth_tb_lvds.v"
vhdl work "lvds_tx_rx_merge.vhd"
vhdl work "lvds_dcm.vhd"
vhdl work "lvds_bist_top.vhd"