test_lvds_tx.v

FPGA之间的LVDS传输

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:02:53 08/20/2008
// Design Name:   DDR_6TO1_16CHAN_RT_TX
// Module Name:   E:/ISEworks/LVDS/xapp860/test_lvds_tx.v
// Project Name:  xapp860
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DDR_6TO1_16CHAN_RT_TX
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_lvds_tx;

	// Inputs
	reg TXCLK;
	reg TXCLKDIV;
	reg [95:0] DATA_TO_OSERDES;
	reg RESET;
	reg TRAINING_DONE;
	
	// Inputs
	reg [15:0] DATA_RX_P;
	reg [15:0] DATA_RX_N;
	reg CLOCK_RX_P;
	reg CLOCK_RX_N;
	reg INC_PAD;
	reg DEC_PAD;
	reg RESET;
	reg IDLY_RESET;
	reg IDELAYCTRL_RESET;
	reg BITSLIP_PAD;
	reg CLK200;
	reg RT_MANUAL_DISABLE;

	// Outputs
	wire [15:0] DATA_TX_P;
	wire [15:0] DATA_TX_N;
	wire CLOCK_TX_P;
	wire CLOCK_TX_N;
	
	// Outputs
	wire [95:0] DATA_FROM_ISERDES;
	wire [5:0] TAP_00;
	wire [5:0] TAP_01;
	wire [5:0] TAP_02;
	wire [5:0] TAP_03;
	wire [5:0] TAP_04;
	wire [5:0] TAP_05;
	wire [5:0] TAP_06;
	wire [5:0] TAP_07;
	wire [5:0] TAP_08;
	wire [5:0] TAP_09;
	wire [5:0] TAP_10;
	wire [5:0] TAP_11;
	wire [5:0] TAP_12;
	wire [5:0] TAP_13;
	wire [5:0] TAP_14;
	wire [5:0] TAP_15;
	wire [5:0] TAP_CLK;
	wire TRAINING_DONE;
	wire RXCLK;
	wire RXCLKDIV;
	wire IDELAY_READY;

	// Instantiate the Unit Under Test (UUT)
	DDR_6TO1_16CHAN_RT_TX uut (
		.DATA_TX_P(DATA_TX_P), 
		.DATA_TX_N(DATA_TX_N), 
		.CLOCK_TX_P(CLOCK_TX_P), 
		.CLOCK_TX_N(CLOCK_TX_N), 
		.TXCLK(TXCLK), 
		.TXCLKDIV(TXCLKDIV), 
		.DATA_TO_OSERDES(DATA_TO_OSERDES), 
		.RESET(RESET), 
		.TRAINING_DONE(TRAINING_DONE)
	);
	
	// Instantiate the Unit Under Test (UUT)
	DDR_6TO1_16CHAN_RT_RX uut (
		.DATA_RX_P(DATA_RX_P), 
		.DATA_RX_N(DATA_RX_N), 
		.CLOCK_RX_P(CLOCK_RX_P), 
		.CLOCK_RX_N(CLOCK_RX_N), 
		.INC_PAD(INC_PAD), 
		.DEC_PAD(DEC_PAD), 
		.DATA_FROM_ISERDES(DATA_FROM_ISERDES), 
		.RESET(RESET), 
		.IDLY_RESET(IDLY_RESET), 
		.IDELAYCTRL_RESET(IDELAYCTRL_RESET), 
		.BITSLIP_PAD(BITSLIP_PAD), 
		.CLK200(CLK200), 
		.TAP_00(TAP_00), 
		.TAP_01(TAP_01), 
		.TAP_02(TAP_02), 
		.TAP_03(TAP_03), 
		.TAP_04(TAP_04), 
		.TAP_05(TAP_05), 
		.TAP_06(TAP_06), 
		.TAP_07(TAP_07), 
		.TAP_08(TAP_08), 
		.TAP_09(TAP_09), 
		.TAP_10(TAP_10), 
		.TAP_11(TAP_11), 
		.TAP_12(TAP_12), 
		.TAP_13(TAP_13), 
		.TAP_14(TAP_14), 
		.TAP_15(TAP_15), 
		.TAP_CLK(TAP_CLK), 
		.TRAINING_DONE(TRAINING_DONE), 
		.RXCLK(RXCLK), 
		.RXCLKDIV(RXCLKDIV), 
		.IDELAY_READY(IDELAY_READY), 
		.RT_MANUAL_DISABLE(RT_MANUAL_DISABLE)
	);

	initial begin
		// Initialize Inputs
		TXCLK = 0;
		TXCLKDIV = 0;
		DATA_TO_OSERDES = 0;
		RESET = 0;
		TRAINING_DONE = 0;


		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule