test_rx.vhd

FPGA之间的LVDS传输

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:05:53 08/20/2008
-- Design Name:   
-- Module Name:   E:/ISEworks/LVDS/xapp860/test_rx.vhd
-- Project Name:  xapp860
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DDR_6TO1_16CHAN_RT_RX
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY test_rx IS
END test_rx;
 
ARCHITECTURE behavior OF test_rx IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DDR_6TO1_16CHAN_RT_RX
    PORT(
         DATA_RX_P : IN  std_logic_vector(15 downto 0);
         DATA_RX_N : IN  std_logic_vector(15 downto 0);
         CLOCK_RX_P : IN  std_logic;
         CLOCK_RX_N : IN  std_logic;
         INC_PAD : IN  std_logic;
         DEC_PAD : IN  std_logic;
         DATA_FROM_ISERDES : OUT  std_logic_vector(95 downto 0);
         RESET : IN  std_logic;
         IDLY_RESET : IN  std_logic;
         IDELAYCTRL_RESET : IN  std_logic;
         BITSLIP_PAD : IN  std_logic;
         CLK200 : IN  std_logic;
         TAP_00 : OUT  std_logic_vector(5 downto 0);
         TAP_01 : OUT  std_logic_vector(5 downto 0);
         TAP_02 : OUT  std_logic_vector(5 downto 0);
         TAP_03 : OUT  std_logic_vector(5 downto 0);
         TAP_04 : OUT  std_logic_vector(5 downto 0);
         TAP_05 : OUT  std_logic_vector(5 downto 0);
         TAP_06 : OUT  std_logic_vector(5 downto 0);
         TAP_07 : OUT  std_logic_vector(5 downto 0);
         TAP_08 : OUT  std_logic_vector(5 downto 0);
         TAP_09 : OUT  std_logic_vector(5 downto 0);
         TAP_10 : OUT  std_logic_vector(5 downto 0);
         TAP_11 : OUT  std_logic_vector(5 downto 0);
         TAP_12 : OUT  std_logic_vector(5 downto 0);
         TAP_13 : OUT  std_logic_vector(5 downto 0);
         TAP_14 : OUT  std_logic_vector(5 downto 0);
         TAP_15 : OUT  std_logic_vector(5 downto 0);
         TAP_CLK : OUT  std_logic_vector(5 downto 0);
         TRAINING_DONE : OUT  std_logic;
         RXCLK : OUT  std_logic;
         RXCLKDIV : OUT  std_logic;
         IDELAY_READY : OUT  std_logic;
         RT_MANUAL_DISABLE : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal DATA_RX_P : std_logic_vector(15 downto 0) := (others => '0');
   signal DATA_RX_N : std_logic_vector(15 downto 0) := (others => '0');
   signal CLOCK_RX_P : std_logic := '0';
   signal CLOCK_RX_N : std_logic := '0';
   signal INC_PAD : std_logic := '0';
   signal DEC_PAD : std_logic := '0';
   signal RESET : std_logic := '0';
   signal IDLY_RESET : std_logic := '0';
   signal IDELAYCTRL_RESET : std_logic := '0';
   signal BITSLIP_PAD : std_logic := '0';
   signal CLK200 : std_logic := '0';
   signal RT_MANUAL_DISABLE : std_logic := '0';

 	--Outputs
   signal DATA_FROM_ISERDES : std_logic_vector(95 downto 0);
   signal TAP_00 : std_logic_vector(5 downto 0);
   signal TAP_01 : std_logic_vector(5 downto 0);
   signal TAP_02 : std_logic_vector(5 downto 0);
   signal TAP_03 : std_logic_vector(5 downto 0);
   signal TAP_04 : std_logic_vector(5 downto 0);
   signal TAP_05 : std_logic_vector(5 downto 0);
   signal TAP_06 : std_logic_vector(5 downto 0);
   signal TAP_07 : std_logic_vector(5 downto 0);
   signal TAP_08 : std_logic_vector(5 downto 0);
   signal TAP_09 : std_logic_vector(5 downto 0);
   signal TAP_10 : std_logic_vector(5 downto 0);
   signal TAP_11 : std_logic_vector(5 downto 0);
   signal TAP_12 : std_logic_vector(5 downto 0);
   signal TAP_13 : std_logic_vector(5 downto 0);
   signal TAP_14 : std_logic_vector(5 downto 0);
   signal TAP_15 : std_logic_vector(5 downto 0);
   signal TAP_CLK : std_logic_vector(5 downto 0);
   signal TRAINING_DONE : std_logic;
   signal RXCLK : std_logic;
   signal RXCLKDIV : std_logic;
   signal IDELAY_READY : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DDR_6TO1_16CHAN_RT_RX PORT MAP (
          DATA_RX_P => DATA_RX_P,
          DATA_RX_N => DATA_RX_N,
          CLOCK_RX_P => CLOCK_RX_P,
          CLOCK_RX_N => CLOCK_RX_N,
          INC_PAD => INC_PAD,
          DEC_PAD => DEC_PAD,
          DATA_FROM_ISERDES => DATA_FROM_ISERDES,
          RESET => RESET,
          IDLY_RESET => IDLY_RESET,
          IDELAYCTRL_RESET => IDELAYCTRL_RESET,
          BITSLIP_PAD => BITSLIP_PAD,
          CLK200 => CLK200,
          TAP_00 => TAP_00,
          TAP_01 => TAP_01,
          TAP_02 => TAP_02,
          TAP_03 => TAP_03,
          TAP_04 => TAP_04,
          TAP_05 => TAP_05,
          TAP_06 => TAP_06,
          TAP_07 => TAP_07,
          TAP_08 => TAP_08,
          TAP_09 => TAP_09,
          TAP_10 => TAP_10,
          TAP_11 => TAP_11,
          TAP_12 => TAP_12,
          TAP_13 => TAP_13,
          TAP_14 => TAP_14,
          TAP_15 => TAP_15,
          TAP_CLK => TAP_CLK,
          TRAINING_DONE => TRAINING_DONE,
          RXCLK => RXCLK,
          RXCLKDIV => RXCLKDIV,
          IDELAY_READY => IDELAY_READY,
          RT_MANUAL_DISABLE => RT_MANUAL_DISABLE
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
  -- constant CLK200_period := 5ns;
 
   CLK200_process :process
   begin
		CLK200 <= '0';
		wait for 5 ns;
		CLK200 <= '1';
		wait for 5 ns;
   end process;
 

  

END;