hdpdeps.ref

FPGA之间的LVDS传输

AR work/lvds_dcm/BEHAVIORAL 1231683572 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_dcm.vhd \
      EN work/lvds_dcm 1231683571 CP BUFGCE CP IBUFG CP BUFG CP DCM_ADV
FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_tx_rx_merge.vhd 2008/12/03.17:18:08 K.37
EN work/lvds_tx_rx_merge 1231683573 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_tx_rx_merge.vhd \
      PB ieee/std_logic_1164 1209777529 PB ieee/std_logic_arith 1209777530 \
      PB ieee/STD_LOGIC_UNSIGNED 1209777531
AR work/lvds_tx_rx_merge/translated 1231683574 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/lvds_tx_rx_merge.vhd \
      EN work/lvds_tx_rx_merge 1231683573 CP DDR_6TO1_16CHAN_RT_RX \
      CP DDR_6TO1_16CHAN_RT_TX
FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RESOURCE_SHARING_CONTROL.vhd 2008/12/03.14:10:25 K.37
EN work/RESOURCE_SHARING_CONTROL 1231683559 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RESOURCE_SHARING_CONTROL.vhd \
      PB ieee/std_logic_1164 1209777529 PB ieee/std_logic_arith 1209777530 \
      PB ieee/STD_LOGIC_UNSIGNED 1209777531 LB unisim PH unisim/VCOMPONENTS 1212040723
AR work/RESOURCE_SHARING_CONTROL/translated 1231683560 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RESOURCE_SHARING_CONTROL.vhd \
      EN work/RESOURCE_SHARING_CONTROL 1231683559 CP count_to_128 CP count_to_16x
FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
EN work/RT_WINDOW_MONITOR 1231683563 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RT_WINDOW_MONITOR.vhd \
      PB ieee/std_logic_1164 1209777529 PB ieee/std_logic_arith 1209777530 \
      PB ieee/STD_LOGIC_UNSIGNED 1209777531 LB unisim PH unisim/VCOMPONENTS 1212040723
AR work/RT_WINDOW_MONITOR/translated 1231683564 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/RT_WINDOW_MONITOR.vhd \
      EN work/RT_WINDOW_MONITOR 1231683563 CP FDR CP count_to_128 CP FDRE
FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37
EN work/seven_bit_reg_w_ce 1231683551 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/seven_bit_reg_w_ce.vhd \
      PB ieee/std_logic_1164 1209777529 PB ieee/std_logic_arith 1209777530 \
      PB ieee/STD_LOGIC_UNSIGNED 1209777531 LB unisim PH unisim/VCOMPONENTS 1212040723
AR work/seven_bit_reg_w_ce/translated 1231683552 \
      FL E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/seven_bit_reg_w_ce.vhd \
      EN work/seven_bit_reg_w_ce 1231683551 CP FDRE
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/BIT_ALIGN_MACHINE.vhd 2008/08/21.17:16:10 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/count_to_128.vhd 2006/08/15.15:03:10 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/count_to_16x.vhd 2008/08/22.15:42:18 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/COUNT_TO_64.vhd 2008/08/21.16:18:32 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/DDR_6TO1_16CHAN_RT_RX.vhd 2008/11/04.11:38:28 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/DDR_6TO1_16CHAN_RT_TX.vhd 2008/11/03.21:32:08 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/fifo_rx.vhd 2008/08/23.15:57:04 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/fifo_tx.vhd 2008/08/23.15:53:56 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/lvds_bist_top.vhd 2008/11/04.16:18:32 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/lvds_dcm.vhd 2008/09/18.09:54:52 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/lvds_tx_rx_merge.vhd 2008/09/19.14:32:38 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/RESOURCE_SHARING_CONTROL.vhd 2008/11/04.11:39:54 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
FL E:/LVDS/LVDS_4to1-rx-AMC-v1.0/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/BIT_ALIGN_MACHINE.vhd 2008/08/21.17:16:10 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/count_to_128.vhd 2006/08/15.15:03:10 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/count_to_16x.vhd 2008/08/22.15:42:18 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/COUNT_TO_64.vhd 2008/08/21.16:18:32 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/DDR_6TO1_16CHAN_RT_RX.vhd 2008/11/11.14:35:58 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/DDR_6TO1_16CHAN_RT_TX.vhd 2008/11/07.10:51:42 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/fifo_rx.vhd 2008/08/23.15:57:04 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/fifo_tx.vhd 2008/08/23.15:53:56 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/lvds_bist_top.vhd 2008/11/08.14:02:39 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/lvds_dcm.vhd 2008/11/08.14:01:28 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/lvds_tx_rx_merge.vhd 2008/09/19.14:32:38 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/RESOURCE_SHARING_CONTROL.vhd 2008/11/04.11:39:54 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
FL E:/LVDS/LVDS_Serdes_List_rx/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/BIT_ALIGN_MACHINE.vhd 2008/08/21.17:16:10 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/count_to_128.vhd 2006/08/15.15:03:10 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/count_to_16x.vhd 2008/08/22.15:42:18 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/COUNT_TO_64.vhd 2008/08/21.16:18:32 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/DDR_6TO1_16CHAN_RT_RX.vhd 2008/11/29.17:25:58 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/DDR_6TO1_16CHAN_RT_TX.vhd 2008/11/07.10:51:42 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/fifo_rx.vhd 2008/08/23.15:57:04 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/fifo_tx.vhd 2008/08/23.15:53:56 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/lvds_bist_top.vhd 2008/11/08.14:02:39 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/lvds_dcm.vhd 2008/11/08.14:01:28 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/lvds_tx_rx_merge.vhd 2008/09/19.14:32:38 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/RESOURCE_SHARING_CONTROL.vhd 2008/11/29.17:38:24 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/BIT_ALIGN_MACHINE.vhd 2008/08/21.17:16:10 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/count_to_128.vhd 2006/08/15.15:03:10 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/count_to_16x.vhd 2008/08/22.15:42:18 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/COUNT_TO_64.vhd 2008/08/21.16:18:32 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/DDR_6TO1_16CHAN_RT_RX.vhd 2008/12/03.17:14:43 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/DDR_6TO1_16CHAN_RT_TX.vhd 2008/12/03.17:18:13 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/fifo_rx.vhd 2008/12/03.17:11:45 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/fifo_tx.vhd 2008/12/03.17:11:47 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_bist_top.vhd 2008/12/03.17:11:43 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_dcm.vhd 2008/11/08.14:01:28 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/lvds_tx_rx_merge.vhd 2008/12/03.17:18:08 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/RESOURCE_SHARING_CONTROL.vhd 2008/12/03.14:10:25 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
FL E:/LVDS/SX95/LVDS_Serdes_List_FPGA1/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/BIT_ALIGN_MACHINE.vhd 2008/08/21.17:16:10 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/count_to_128.vhd 2006/08/15.15:03:10 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/count_to_16x.vhd 2008/08/22.15:42:18 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/COUNT_TO_64.vhd 2008/08/21.16:18:32 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/DDR_6TO1_16CHAN_RT_RX.vhd 2008/11/04.11:38:28 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/DDR_6TO1_16CHAN_RT_TX.vhd 2008/11/03.21:32:08 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/fifo_rx.vhd 2008/08/23.15:57:04 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/fifo_tx.vhd 2008/08/23.15:53:56 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/lvds_bist_top.vhd 2008/11/02.21:54:52 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/lvds_dcm.vhd 2008/09/18.09:54:52 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/lvds_tx_rx_merge.vhd 2008/09/19.14:32:38 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/RESOURCE_SHARING_CONTROL.vhd 2008/11/04.11:39:54 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
FL F:/LAB/LVDS/LVDS_4to1-rx-AMC-v1.0/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/BIT_ALIGN_MACHINE.vhd 2008/08/21.17:16:10 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/count_to_128.vhd 2006/08/15.15:03:10 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/count_to_16x.vhd 2008/08/22.15:42:18 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/COUNT_TO_64.vhd 2008/08/21.16:18:32 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/DDR_6TO1_16CHAN_RT_RX.vhd 2008/08/25.17:09:30 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/DDR_6TO1_16CHAN_RT_TX.vhd 2008/09/19.15:00:32 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/fifo_rx.vhd 2008/08/23.15:57:04 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/fifo_tx.vhd 2008/08/23.15:53:56 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/lvds_bist_top.vhd 2008/09/19.20:31:26 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/lvds_dcm.vhd 2008/09/18.09:54:52 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/lvds_tx_rx_merge.vhd 2008/09/19.14:32:38 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/RESOURCE_SHARING_CONTROL.vhd 2008/08/22.15:44:50 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/RT_WINDOW_MONITOR.vhd 2008/08/21.16:18:20 K.37
FL H:/Gbit_fpga/LVDS/LVDS_4to1/seven_bit_reg_w_ce.vhd 2008/08/21.16:18:08 K.37