xapp860.restore

来自「FPGA之间的LVDS传输」· RESTORE 代码 · 共 1,495 行 · 第 1/5 页

      "A" "" "" "" "PROP_xilxBitgCfg_Unused_virtex5" "Pull Down" 
      "A" "" "" "" "PROP_xilxBitgReadBk_Sec" "Enable Readback and Reconfiguration" 
      "A" "" "" "" "PROP_xilxBitgReadBk_Sec_virtex5" "Enable Readback and Reconfiguration" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk" "CCLK" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_Done" "Default (4)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_Done_virtex5" "Default (4)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_DriveDone_virtex5" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut" "Default (5)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_EnOut_virtex5" "Default (5)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle" "Auto" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_MatchCycle_virtex5" "Auto" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL" "Default (NoWait)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelDLL_virtex5" "Default (NoWait)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_RelSet" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_WrtEn_virtex5" "Default (6)" 
      "A" "" "" "" "PROP_xilxBitgStart_Clk_virtex5" "CCLK" 
      "A" "" "" "" "PROP_xilxBitgStart_IntDone" "false" 
      "A" "" "" "" "PROP_xilxBitgStart_IntDone_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapAllowLogicOpt" "false" 
      "A" "" "" "" "PROP_xilxMapCoverMode" "Area" 
      "A" "" "" "" "PROP_xilxMapDisableRegOrdering" "false" 
      "A" "" "" "" "PROP_xilxMapMaxCompression_virtex5" "false" 
      "A" "" "" "" "PROP_xilxMapPackRegInto" "Off" 
      "A" "" "" "" "PROP_xilxMapReplicateLogic" "true" 
      "A" "" "" "" "PROP_xilxMapReportDetail" "false" 
      "A" "" "" "" "PROP_xilxMapSliceLogicInUnusedBRAMs" "false" 
      "A" "" "" "" "PROP_xilxMapTimingDrivenPacking" "false" 
      "A" "" "" "" "PROP_xilxMapTrimUnconnSig" "true" 
      "A" "" "" "" "PROP_xilxNgdbldIOPads" "false" 
      "A" "" "" "" "PROP_xilxNgdbldMacro" "" 
      "A" "" "" "" "PROP_xilxNgdbldNTType" "Timestamp" 
      "A" "" "" "" "PROP_xilxNgdbldPresHierarchy" "false" 
      "A" "" "" "" "PROP_xilxNgdbldUR" "" 
      "A" "" "" "" "PROP_xilxNgdbldUnexpBlks" "false" 
      "A" "" "" "" "PROP_xilxNgdbld_AUL" "false" 
      "A" "" "" "" "PROP_xilxPARplacerCostTable" "1" 
      "A" "" "" "" "PROP_xilxPARplacerEffortLevel" "None" 
      "A" "" "" "" "PROP_xilxPARrouterEffortLevel" "None" 
      "A" "" "" "" "PROP_xilxPARstrat" "Normal Place and Route" 
      "A" "" "" "" "PROP_xilxPARuseBondedIO" "false" 
      "A" "" "" "" "PROP_xilxPostTrceAdvAna" "false" 
      "A" "" "" "" "PROP_xilxPostTrceEndpointPath" "" 
      "A" "" "" "" "PROP_xilxPostTrceRpt" "Verbose Report" 
      "A" "" "" "" "PROP_xilxPostTrceRptLimit" "3" 
      "A" "" "" "" "PROP_xilxPostTrceStamp" "" 
      "A" "" "" "" "PROP_xilxPostTrceTSIFile" "" 
      "A" "" "" "" "PROP_xilxPostTrceUncovPath" "" 
      "A" "" "" "" "PROP_xilxPreTrceAdvAna" "false" 
      "A" "" "" "" "PROP_xilxPreTrceEndpointPath" "" 
      "A" "" "" "" "PROP_xilxPreTrceRpt" "Verbose Report" 
      "A" "" "" "" "PROP_xilxPreTrceRptLimit" "3" 
      "A" "" "" "" "PROP_xilxPreTrceUncovPath" "" 
      "A" "" "" "" "PROP_xilxSynthAddIObuf" "true" 
      "A" "" "" "" "PROP_xilxSynthGlobOpt" "AllClockNets" 
      "A" "" "" "" "PROP_xilxSynthKeepHierarchy" "Yes" 
      "A" "" "" "" "PROP_xilxSynthKeepHierarchy_CPLD" "Yes" 
      "A" "" "" "" "PROP_xilxSynthMacroPreserve" "true" 
      "A" "" "" "" "PROP_xilxSynthRegBalancing" "No" 
      "A" "" "" "" "PROP_xilxSynthRegDuplication" "true" 
      "A" "" "" "" "PROP_xilxSynthXORPreserve" "true" 
      "A" "" "" "" "PROP_xilxTriStateBuffTXMode" "Off" 
      "A" "" "" "" "PROP_xstAsynToSync" "false" 
      "A" "" "" "" "PROP_xstAutoBRAMPacking" "false" 
      "A" "" "" "" "PROP_xstBRAMUtilRatio" "100" 
      "A" "" "" "" "PROP_xstBusDelimiter" "<>" 
      "A" "" "" "" "PROP_xstCase" "Maintain" 
      "A" "" "" "" "PROP_xstCoresSearchDir" "" 
      "A" "" "" "" "PROP_xstCrossClockAnalysis" "false" 
      "A" "" "" "" "PROP_xstDSPUtilRatio" "100" 
      "A" "" "" "" "PROP_xstDSPUtilRatio_virtex5" "100" 
      "A" "" "" "" "PROP_xstEquivRegRemoval" "true" 
      "A" "" "" "" "PROP_xstFsmStyle" "LUT" 
      "A" "" "" "" "PROP_xstGenerateRTLNetlist" "Yes" 
      "A" "" "" "" "PROP_xstGenericsParameters" "" 
      "A" "" "" "" "PROP_xstHierarchySeparator" "/" 
      "A" "" "" "" "PROP_xstIniFile" "" 
      "A" "" "" "" "PROP_xstLUTCombining_virtex5" "No" 
      "A" "" "" "" "PROP_xstLibSearchOrder" "" 
      "A" "" "" "" "PROP_xstNetlistHierarchy" "As Optimized" 
      "A" "" "" "" "PROP_xstOptimizeInsPrimtives" "false" 
      "A" "" "" "" "PROP_xstPackIORegister" "Auto" 
      "A" "" "" "" "PROP_xstPowerOptimization" "false" 
      "A" "" "" "" "PROP_xstPowerOptimization_virtex5" "false" 
      "A" "" "" "" "PROP_xstReadCores" "true" 
      "A" "" "" "" "PROP_xstSlicePacking" "true" 
      "A" "" "" "" "PROP_xstSliceUtilRatio" "100" 
      "A" "" "" "" "PROP_xstTristate2Logic" "Yes" 
      "A" "" "" "" "PROP_xstUseClockEnable" "Yes" 
      "A" "" "" "" "PROP_xstUseSyncReset" "Yes" 
      "A" "" "" "" "PROP_xstUseSyncSet" "Yes" 
      "A" "" "" "" "PROP_xstUseSynthConstFile" "true" 
      "A" "" "" "" "PROP_xstUserCompileList" "" 
      "A" "" "" "" "PROP_xstVeriIncludeDir_Global" "" 
      "A" "" "" "" "PROP_xstVerilog2001" "true" 
      "A" "" "" "" "PROP_xstVerilogMacros" "" 
      "A" "" "" "" "PROP_xstWorkDir" "./xst" 
      "A" "" "" "" "PROP_xstWriteTimingConstraints" "false" 
      "A" "" "" "" "PROP_xst_otherCmdLineOptions" "" 
      "A" "" "" "PROP_SteCreatedBy" "PROP_SteCreatedBy" "" 
      "A" "AutoGeneratedView" "VIEW_Post-MapPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-ParPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_Post-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_PostAbstractSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-MapPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-ParPreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_TBWPost-TranslatePreSimulation" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_TopDesignUnit" "" 
      "A" "AutoGeneratedView" "VIEW_XSTPreSynthesis" "" "PROP_xstVeriIncludeDir" "" 
      "B" "" "" "" "PROPEXT_SynthFrequencySyn_virtex" "0.0" 
      "B" "" "" "" "PROPEXT_SynthFrequencySyn_virtex5" "0.0" 
      "B" "" "" "" "PROPEXT_mapTimingMode_virtex5" "Performance Evaluation" 
      "B" "" "" "" "PROPEXT_parGenAsyDlyRpt_virtex5" "false" 
      "B" "" "" "" "PROPEXT_parGenClkRegionRpt_virtex5" "false" 
      "B" "" "" "" "PROPEXT_parGenSimModel_virtex5" "false" 
      "B" "" "" "" "PROPEXT_parGenTimingRpt_virtex5" "true" 
      "B" "" "" "" "PROPEXT_parMpprNodelistFile_virtex5" "" 
      "B" "" "" "" "PROPEXT_parMpprParIterations_virtex5" "3" 
      "B" "" "" "" "PROPEXT_parMpprResultsDirectory_virtex5" "" 
      "B" "" "" "" "PROPEXT_parMpprResultsToSave_virtex5" "" 
      "B" "" "" "" "PROPEXT_parPowerReduction_virtex5" "false" 
      "B" "" "" "" "PROPEXT_xilxPAReffortLevel_virtex5" "Standard" 
      "B" "" "" "" "PROP_AceActiveName" "" 
      "B" "" "" "" "PROP_DevFamily" "Virtex5" 
      "B" "" "" "" "PROP_FitterOptimization_xpla3" "Density" 
      "B" "" "" "" "PROP_ISimCustomCompilationOrderFile" "" 
      "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tb" "" 
      "B" "" "" "" "PROP_ISimCustomSimCmdFileName_behav_tbw" "" 
      "B" "" "" "" "PROP_ISimCustomSimCmdFileName_gen_tbw" "" 
      "B" "" "" "" "PROP_ISimCustomSimCmdFileName_launch" "" 
      "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tb" "" 
      "B" "" "" "" "PROP_ISimCustomSimCmdFileName_par_tbw" "" 
      "B" "" "" "" "PROP_ISimGenVCDFile_par_tb" "false" 
      "B" "" "" "" "PROP_ISimGenVCDFile_par_tbw" "false" 
      "B" "" "" "" "PROP_ISimSimulationRun_behav_tb" "true" 
      "B" "" "" "" "PROP_ISimSimulationRun_behav_tbw" "true" 
      "B" "" "" "" "PROP_ISimSimulationRun_par_tb" "true" 
      "B" "" "" "" "PROP_ISimSimulationRun_par_tbw" "true" 
      "B" "" "" "" "PROP_MapEffortLevel" "Medium" 
      "B" "" "" "" "PROP_MapEquivalentRegisterRemoval" "true" 
      "B" "" "" "" "PROP_MapExtraEffort_virtex5" "None" 
      "B" "" "" "" "PROP_MapLogicOptimization" "false" 
      "B" "" "" "" "PROP_MapPlacerCostTable" "1" 
      "B" "" "" "" "PROP_MapPowerActivityFile_virtex5" "" 
      "B" "" "" "" "PROP_MapPowerReduction" "false" 
      "B" "" "" "" "PROP_MapRegDuplication" "false" 
      "B" "" "" "" "PROP_MapRetiming" "false" 
      "B" "" "" "" "PROP_ModelSimConfigName" "Default" 
      "B" "" "" "" "PROP_ModelSimDataWin" "false" 
      "B" "" "" "" "PROP_ModelSimListWin" "false" 
      "B" "" "" "" "PROP_ModelSimProcWin" "false" 
      "B" "" "" "" "PROP_ModelSimSignalWin" "true" 
      "B" "" "" "" "PROP_ModelSimSimRes" "Default (1 ps)" 
      "B" "" "" "" "PROP_ModelSimSimRunTime_tb" "1000ns" 
      "B" "" "" "" "PROP_ModelSimSimRunTime_tbw" "1000ns" 
      "B" "" "" "" "PROP_ModelSimSourceWin" "false" 
      "B" "" "" "" "PROP_ModelSimStructWin" "true" 
      "B" "" "" "" "PROP_ModelSimUutInstName_postFit" "UUT" 
      "B" "" "" "" "PROP_ModelSimUutInstName_postMap" "UUT" 
      "B" "" "" "" "PROP_ModelSimUutInstName_postPar" "UUT" 
      "B" "" "" "" "PROP_ModelSimVarsWin" "false" 
      "B" "" "" "" "PROP_ModelSimWaveWin" "true" 
      "B" "" "" "" "PROP_PrecNumOfCriticalPaths" "1" 
      "B" "" "" "" "PROP_PrecNumOfSumPaths" "10" 
      "B" "" "" "" "PROP_SimCustom_behav" "" 
      "B" "" "" "" "PROP_SimCustom_launchMSim" "" 
      "B" "" "" "" "PROP_SimCustom_postMap" "" 
      "B" "" "" "" "PROP_SimCustom_postPar" "" 
      "B" "" "" "" "PROP_SimCustom_postXlate" "" 
      "B" "" "" "" "PROP_SimGenVcdFile" "false" 
      "B" "" "" "" "PROP_SimModelRenTopLevInstTo" "UUT" 
      "B" "" "" "" "PROP_SimSyntax" "93" 
      "B" "" "" "" "PROP_SimUseExpDeclOnly" "true" 
      "B" "" "" "" "PROP_SimUserCompileList_behav" "" 
      "B" "" "" "" "PROP_Simulator" "Modelsim-SE Mixed" 
      "B" "" "" "" "PROP_SmartGuideFileName" "lvds_bist_top_guide.ncd" 
      "B" "" "" "" "PROP_SynthConstraintsFile" "" 
      "B" "" "" "" "PROP_SynthMuxStyle" "Auto" 
      "B" "" "" "" "PROP_SynthRAMStyle" "Auto" 
      "B" "" "" "" "PROP_XPowerOptAdvancedVerboseRpt" "false" 
      "B" "" "" "" "PROP_XPowerOptMaxNumberLines" "1000" 
      "B" "" "" "" "PROP_XplorerEnableRetiming" "true" 
      "B" "" "" "" "PROP_XplorerNumIterations" "7" 
      "B" "" "" "" "PROP_XplorerOtherCmdLineOptions" "" 
      "B" "" "" "" "PROP_XplorerRunType" "Yes" 
      "B" "" "" "" "PROP_XplorerWarnToBackup" "true" 
      "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt" "false" 
      "B" "" "" "" "PROP_bitgen_Encrypt_Encrypt_virtex5" "false" 
      "B" "" "" "" "PROP_impactBaud" "None" 
      "B" "" "" "" "PROP_impactConfigFileName" "" 
      "B" "" "" "" "PROP_impactConfigMode" "None" 
      "B" "" "" "" "PROP_impactPort" "Auto - default" 
      "B" "" "" "" "PROP_mapTimingMode" "Non Timing Driven" 
      "B" "" "" "" "PROP_mpprViewPadRptForSelRslt" "" 
      "B" "" "" "" "PROP_mpprViewParRptForSelRslt" "" 
      "B" "" "" "" "PROP_parGenAsyDlyRpt" "false" 
      "B" "" "" "" "PROP_parGenClkRegionRpt" "false" 
      "B" "" "" "" "PROP_parGenSimModel" "false" 
      "B" "" "" "" "PROP_parGenTimingRpt" "true" 
      "B" "" "" "" "PROP_parMpprNodelistFile" "" 
      "B" "" "" "" "PROP_parMpprParIterations" "3" 
      "B" "" "" "" "PROP_parMpprResultsDirectory" "" 
      "B" "" "" "" "PROP_parMpprResultsToSave" "" 
      "B" "" "" "" "PROP_parPowerReduction" "false" 
      "B" "" "" "" "PROP_parTimingMode" "Performance Evaluation" 
      "B" "" "" "" "PROP_vcom_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_vlog_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_vsim_otherCmdLineOptions" "" 
      "B" "" "" "" "PROP_xcpldFitDesInReg_xbr" "true" 
      "B" "" "" "" "PROP_xcpldFitDesPtermLmt_xbr" "28" 
      "B" "" "" "" "PROP_xilxBitgCfg_BPI_First_Read_Cycle_virtex5" "2" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_DbgBitStr_virtex5" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex5" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile" "false" 
      "B" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex5" "false" 
      "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr" "false" 
      "B" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex5" "false" 
      "B" "" "" "" "PROP_xilxMapPackfactor" "100" 
      "B" "" "" "" "PROP_xilxMapPackfactor_virtex5" "0" 
      "B" "" "" "" "PROP_xilxPAReffortLevel" "Standard" 
      "B" "" "" "" "PROP_xstMoveFirstFfStage" "true" 
      "B" "" "" "" "PROP_xstMoveLastFfStage" "true" 
      "B" "" "" "" "PROP_xstROMStyle" "Auto" 
      "B" "" "" "" "PROP_xstSafeImplement" "No" 
      "B" "AutoGeneratedView" "VIEW_Map" "" "PROP_ParSmartGuideFileName" "lvds_bist_top_guide.ncd" 
      "B" "AutoGeneratedView" "VIEW_Translation" "" "PROP_MapSmartGuideFileName" "lvds_bist_top_guide.ncd" 
      "C" "" "" "" "PROPEXT_parPowerActivityFile_virtex5" "" 
      "C" "" "" "" "PROPEXT_xilxPARextraEffortLevel_virtex5" "None" 
      "C" "" "" "" "PROP_CompxlibLang" "All" 
      "C" "" "" "" "PROP_CompxlibSimPath" "c:/Modeltech_6.1f/win32" 
      "C" "" "" "" "PROP_CompxlibSmartModels" "true" 
      "C" "" "" "" "PROP_CompxlibUpdateIniForSmartModel" "false" 
      "C" "" "" "" "PROP_DevDevice" "xc5vfx130t" 
      "C" "" "" "" "PROP_DevFamilyPMName" "virtex5" 
      "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tb" "1000 ns" 
      "C" "" "" "" "PROP_ISimSimulationRunTime_behav_tbw" "1000 ns" 
      "C" "" "" "" "PROP_ISimSimulationRunTime_par_tb" "1000 ns" 
      "C" "" "" "" "PROP_ISimSimulationRunTime_par_tbw" "1000 ns" 
      "C" "" "" "" "PROP_ISimVCDFileName_par_tb" "xpower.vcd" 
      "C" "" "" "" "PROP_ISimVCDFileName_par_tbw" "xpower.vcd" 
      "C" "" "" "" "PROP_MapExtraEffort" "None" 
      "C" "" "" "" "PROP_MapPowerActivityFile" "" 
      "C" "" "" "" "PROP_SimModelGenMultiHierFile" "false" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key0" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key0_virtex5" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key1" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key2" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key3" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key4" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_key5" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_keyFile" "" 
      "C" "" "" "" "PROP_bitgen_Encrypt_keyFile_virtex5" "" 
      "C" "" "" "" "PROP_parPowerActivityFile" "" 
      "C" "" "" "" "PROP_xilxBitgCfg_Fallback_Reconfig_virtex5" "Enable" 
      "C" "" "" "" "PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2" "false" 
      "C" "" "" "" "PROP_xilxPARextraEffortLevel" "None" 
      "D" "" "" "" "PROP_CompxlibUni9000Lib" "true" 
      "D" "" "" "" "PROP_CompxlibUniSimLib" "true" 
      "D" "" "" "" "PROP_DevPackage" "ff1738" 
      "D" "" "" "" "PROP_Synthesis_Tool" "XST (VHDL/Verilog)" 
      "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2" "false" 
      "D" "" "" "" "PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2" "false" 
      "D" "" "" "" "PROP_xilxBitgReadBk_GenBitStr_virtex2" "false" 
      "D" "" "" "" "PROP_xilxSynthAddBufr" "32" 
      "E" "" "" "" "PROP_DevSpeed" "-1" 
      "E" "" "" "" "PROP_PreferredLanguage" "VHDL" 
      "F" "" "" "" "PROP_ChangeDevSpeed" "-1" 
      "F" "" "" "" "PROP_HdlTemplateLang" "VHDL" 
      "F" "" "" "" "PROP_SimModelTarget" "VHDL" 
      "F" "" "" "" "PROP_coregenFuncModelTargetLang" "VHDL" 
      "F" "" "" "" "PROP_hdlInstTempTargetLang" "VHDL" 
      "F" "" "" "" "PROP_schFuncModelTargetLang" "VHDL" 
      "F" "" "" "" "PROP_schInstTempTargetLang" "VHDL" 
      "F" "" "" "" "PROP_sysgenInstTempTargetLang" "VHDL" 
      "F" "" "" "" "PROP_tbwTestbenchTargetLang" "VHDL" 
      "F" "" "" "" "PROP_xawHdlSourceTargetLang" "VHDL" 
      "F" "" "" "" "PROP_xilxPostTrceSpeed" "-1" 
      "F" "" "" "" "PROP_xilxPreTrceSpeed" "-1" 
      "F" "" "" "" "PROP_xmpInstTempTargetLang" "VHDL" 
      "G" "" "" "" "PROP_HdlTemplateName" "xapp860.vhd" 
      "G" "" "" "" "PROP_SimModelAutoInsertGlblModuleInNetlist" "true" 
      "G" "" "" "" "PROP_SimModelGenArchOnly" "false" 
      "G" "" "" "" "PROP_SimModelIncSdfAnnInVerilogFile" "true" 
      "G" "" "" "" "PROP_SimModelIncSimprimInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelIncUnisimInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelIncUselibDirInVerilogFile" "false" 
      "G" "" "" "" "PROP_SimModelNoEscapeSignal" "false" 
      "G" "" "" "" "PROP_SimModelOutputExtIdent" "false" 
      "G" "" "" "" "PROP_SimModelRenTopLevArchTo" "Structure" 
      "G" "" "" "" "PROP_SimModelRenTopLevMod" "" 
      "G" "" "" "" "PROP_bencherPostMapTestbenchName" "lvds_vhd_tb.map_vhw" 
      "G" "" "" "" "PROP_bencherPostParTestbenchName" "lvds_bist_top_tb.timesim_vhw" 
      "G" "" "" "" "PROP_bencherPostXlateTestbenchName" "lvds_vhd_tb.translate_vhw" 
      "G" "" "" "" "PROP_netgenPostMapSimModelName" "lvds_bist_top_map.vhd" 
      "G" "" "" "" "PROP_netgenPostParSimModelName" "lvds_bist_top_timesim.vhd" 
      "G" "" "" "" "PROP_netgenPostSynthesisSimModelName" "lvds_bist_top_synt